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ICS9179YG-03LF-T

Low Skew Clock Driver, 9179 Series, 10 True Output(s), 0 Inverted Output(s), PDSO28, 6.10 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28

器件类别:逻辑    逻辑   

厂商名称:IDT (Integrated Device Technology)

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
IDT (Integrated Device Technology)
零件包装代码
TSSOP
包装说明
TSSOP,
针数
28
Reach Compliance Code
compliant
系列
9179
输入调节
STANDARD
JESD-30 代码
R-PDSO-G28
JESD-609代码
e3
长度
9.7 mm
逻辑集成电路类型
LOW SKEW CLOCK DRIVER
功能数量
1
反相输出次数
端子数量
28
实输出次数
10
最高工作温度
70 °C
最低工作温度
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)
260
传播延迟(tpd)
5.5 ns
认证状态
Not Qualified
Same Edge Skew-Max(tskwd)
0.25 ns
座面最大高度
1.2 mm
最大供电电压 (Vsup)
3.465 V
最小供电电压 (Vsup)
3.135 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
温度等级
COMMERCIAL
端子面层
MATTE TIN
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
6.1 mm
最小 fmax
133 MHz
Base Number Matches
1
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Integrated
Circuit
Systems, Inc.
ICS9179-03
Low Skew Fan Out Buffers
General Description
The
ICS9179-03
generates low skew clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumPro. Outputs will handle up to 133MHz clocks.
An output enable is provided for testability.
The device is a buffer with low output to output skew. This is
a Fanout buffer device, not using an internal PLL. This buffer
can also be a feedback to an external PLL stage for phase
synchronization to a master clock. There are a total of ten
outputs, sufficient for feedback to a PLL source and to drive
four small outline DIMM modules (S.O. DIMM) at 2 clocks
each. Or a total of ten outputs as a Fanout buffer from a
common clock source.
The individual clock outputs are addressable through I
2
C to
be enabled, or stopped in a low state for reduced EMI when
the lines are not needed.
Features
Ten High speed, low noise non-inverting buffers for (to
133MHz), clock buffer applications.
Output slew rate faster than 1.5V/ns into 20pF
Supports up to four small outline DIMMS (S.O. DIMM).
Synchronous clocks skew matched to 250 ps window on
OUTPUTs (0:9).
I
2
C Serial Configuration interface to allow individual
OUTPUTs to be stopped low.
Multiple VDD, VSS pins for noise reduction
Tri-state pin for testing
3.0V – 3.7V supply range
28-pin (209 mil) SSOP and (6.1mm) TSSOP package
Block Diagram
Pin Configuration
28-Pin SSOP & TSSOP
0258J 08/29/05
PentiumPro is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9179-03
Pin Descriptions
PIN NUMBER
2, 3
6, 7
22, 23
26, 27
11
18
9
20
14
15
1, 5, 10,
19, 24, 28
4, 8, 12,
16, 17, 21, 25
13
16
P I N NA M E
OUTPUT (0:1)
OUTPUT (2:3)
OUTPUT (4:5)
OUTPUT (6:7)
OUTPUT8
OUTPUT9
BU F _ I N
OE
SDATA
SCLK
VDD (0:5)
GND (0:5)
VDDI
GNDI
TYPE
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
I/O
I/O
PWR
PWR
PWR
PWR
DESCRIPTION
C l o c k o u t p u t s
1
, u s e s V D D 0 , G N D 0
C l o c k o u t p u t s
1
, u s e s V D D 1 , G N D 1
Clock outputs
1
uses VDD2, GND2
Clock output
1
uses VDD3, GND3
Clock output
1
uses VDD4, GND4
Clock output
1
uses VDD5, GND5
Input for buffers
Tri-states all outputs when held LOW. Has internal pull-up.
2
D a t a p i n f o r I
2
C c i r c u i t r y
3
C l o c k p i n f o r I
2
C c i r c u i t r y
3
3.3V Power supply for OUTPUT buffers
Ground for OUTPUT buffers
3.3V Power supply for I
2
C circuitry and internal logic
G r o u n d f o r I
2
C c i r c u i t r y a n d i n t e r n a l l o g i c
Notes:
1.
At power up all ten OUTPUTs are enabled and active.
2.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
3.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
complete platform flexibility.
Power Groups
VDD (0:5), GND (0:5) = Power supply for OUTPUT buffer
VDDI, GNDI = Power supply for I
2
C circuitry
0258J 08/29/05
2
ICS9179-03
Technical Pin Function Descriptions
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for OUTPUT (0:9).
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
OUTPUT (0:9)
These Output Clocks are use to drive Dynamic RAM’s and
are low skew copies of the CPU Clocks. The voltage swing of
the OUTPUTs output is controlled by the supply voltage
that is applied to VDD of the device, operates at 3.3 volts.
I
2
C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I
2
C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I
2
C specification
in Philips I
2
C Peripherals Data Handbook (1996) should be
followed.
BUF_IN
Input for Fanout buffers (OUTPUT 0:9).
OE
OE tristates all outputs when held low.
VDD1
This is the power supply to I
2
C circuitry.
0258J 08/29/05
3
ICS9179-03
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will
acknowledge
each byte
one at a time.
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0258J 08/29/05
4
ICS9179-03
Serial Configuration Command Bitmaps
Byte 0: OUTPUT Clock Register (Default=0)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN#
-
-
-
-
7
6
3
2
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
OUTPUT3
OUTPUT2
OUTPUT1
OUTPUT0
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Note:
PWD = Power-Up Default
Byte 1: OUTPUT Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
27
26
23
22
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
OUTPUT7 (Act/Inact)
OUTPUT6 (Act/Inact)
OUTPUT5 (Act/Inact)
OUTPUT4 (Act/Inact)
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
Byte 2: OUTPUT Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
18
11
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
OUTPUT9 (Act/Inact)
OUTPUT8 (Act/Inact)
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Note:
PWD = Power-Up Default
ICS9179-03 Power Management
The values below are estimates of target specifications.
Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
All static inputs = VDD or GND
3mA
Condition
No Clock Mode
(BUF_IN - VDD1 or GND)
I
2
C Circuitry Active
Active 66MHz
(BUF_IN = 66.66MHz)
Active 100MHz
(BUF_IN = 100.00MHz)
Active 133MHz
(BUF_IN = 133.33MHz)
0258J 08/29/05
Functionality
230mA
360mA
460mA
OE#
0
1
OUTPUT (0:9)
Hi-Z
1 X BUF_IN
5
查看更多>
参数对比
与ICS9179YG-03LF-T相近的元器件有:ICS9179YG-03-T、ICS9179YF-03-T、ICS9179YF-03LF-T。描述及对比如下:
型号 ICS9179YG-03LF-T ICS9179YG-03-T ICS9179YF-03-T ICS9179YF-03LF-T
描述 Low Skew Clock Driver, 9179 Series, 10 True Output(s), 0 Inverted Output(s), PDSO28, 6.10 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28 Low Skew Clock Driver, 9179 Series, 10 True Output(s), 0 Inverted Output(s), PDSO28, 6.10 MM, 0.65 MM PITCH, MO-153, TSSOP-28 Low Skew Clock Driver, 9179 Series, 10 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, MO-150, SSOP-28 Low Skew Clock Driver, 9179 Series, 10 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28
是否无铅 不含铅 含铅 含铅 不含铅
是否Rohs认证 符合 不符合 不符合 符合
零件包装代码 TSSOP TSSOP SSOP SSOP
包装说明 TSSOP, TSSOP, SSOP, SSOP,
针数 28 28 28 28
Reach Compliance Code compliant compliant compliant compliant
系列 9179 9179 9179 9179
输入调节 STANDARD STANDARD STANDARD STANDARD
JESD-30 代码 R-PDSO-G28 R-PDSO-G28 R-PDSO-G28 R-PDSO-G28
JESD-609代码 e3 e0 e0 e3
长度 9.7 mm 9.7 mm 10.2 mm 10.2 mm
逻辑集成电路类型 LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
功能数量 1 1 1 1
端子数量 28 28 28 28
实输出次数 10 10 10 10
最高工作温度 70 °C 70 °C 70 °C 70 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP TSSOP SSOP SSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度) 260 NOT SPECIFIED 225 260
传播延迟(tpd) 5.5 ns 5.5 ns 5.5 ns 5.5 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.25 ns 0.25 ns 0.25 ns 0.25 ns
座面最大高度 1.2 mm 1.2 mm 2 mm 2 mm
最大供电电压 (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V
最小供电电压 (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 MATTE TIN TIN LEAD TIN LEAD MATTE TIN
端子形式 GULL WING GULL WING GULL WING GULL WING
端子节距 0.65 mm 0.65 mm 0.65 mm 0.65 mm
端子位置 DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED 30 30
宽度 6.1 mm 6.1 mm 5.3 mm 5.3 mm
最小 fmax 133 MHz 133 MHz 133 MHz 133 MHz
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) - IDT (Integrated Device Technology)
Base Number Matches 1 1 1 -
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