Integrated
Circuit
Systems, Inc.
ICS9248-56
Frequency Timing Generator for Pentium II Systems
General Description
The
ICS9248-56
is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The
ICS9248-56
employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
Features
•
Generates the following system clocks:
- 2CPU(2.5V) up to 100MHz.
- 6 PCI(3.3V) @ 33.3MHz (Includes one free running).
- 1 REF clks (3.3V) at 14.318MHz.
- 1 Fixed clock at 48MHz
- 1 Fixed clock at 48 or 24MHz
Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
Efficient Power management scheme through stop clocks
and power down modes.
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
28 pin 209mil SSOP and 173mil TSSOP
•
•
•
Block Diagram
•
•
Pin Configuration
28 pin SSOP and TSSOP
Power Groups
VDD, GND = PLL core
VDDREF, GNDREF = REF(0:1), X1, X2
VDDPCI, GNDPCI = PCICLK_F, PCICLK (0:4)
VDD48, GND48 = 48MHz, 48/24MHz
Pentium is a trademark on Intel Corporation.
9248-56 Rev E 12/27/00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-56
Pin Descriptions
Pin number
1
2
3
4
5,6,9,10,11
7
8
12
13
14
15
16
Pin name
GNDREF
X1
X2
PCICLK_F
PCICLK (1:5)
GNDPCI
VDDPCI
VDD48
48 MHz
TS#/48/24MHz
GND48
SEL 100/66#
Type
Power
Input
Output
Output
Output
Power
Power
Power
Output
Output
Power
Input
Description
Ground for 14.318 MHz reference clock outputs
14.318 MHz crystal input
14.318 MHz crystal output
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
3.3 V PCI clock outputs, generating timing requirements for Pentium II
Ground for PCI clock outputs
3.3 V power for the PCI clock outputs
3.3 V power for 48/24 MHz clocks
3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices
3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for testing,
active high = normal operation
Ground for 48/24 MHz clocks
control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is
used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz
frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
selected cases.
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
Isolated 3.3 V power for core
Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
Isolated ground for core
Ground for CPU clock outputs
2.5 V CPU clock outputs
2.5 V power for CPU clock outputs
Power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option.
Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14.
3.3 V power for 14.318 MHz reference clock outputs.
17
PD#
Input
18
19
20
21
22
23,24
25
26
27
28
CPU_STOP#
VDD
PCI-Stop#
GND
GNDL
CPUCLK(1:0)
VDDL
SPREAD#
REF0/SEL48#
VDDREF
Input
Power
Input
Power
Power
Output
Power
Output
Output
Power
2
ICS9248-56
Select Functions
(Functionality determined by TS# and SEL100/66# pin, see below)
Functionality
Tristate
Testmode
CPUCLK
HI - Z
TCLK/2
1
PCI,
PCI_F
HI - Z
TCLK/6
1
REF0
HI - Z
TCLK
1
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
SEL 100/66#
0
0
0
0
1
1
1
1
TS#
0
-
-
1
0
-
-
1
Function
Tri-State
(Reserved)
(Reserved)
Active 66.6MHz CPU, 33.3 PCI
Test Mode
(Reserved)
(Reserved)
Active 100MHz CPU, 33.3 PCI
Power Management
Clock Enable Configuration
C P U _ S TO P # P C I _ S TO P #
X
X
0
0
0
1
1
0
1
1
P W R _ DW N #
0
1
1
1
1
CPUCLK
L ow
Low
Low
100/66.6MHz
100/66.6MHz
PCICLK PCICLK_F
L ow
L ow
Low
33.3MHz
33.3 MHz 33.3MHz
Low
33.3MHz
33.3 MHz 33.3MHz
REF
Stopped
Running
Running
Running
Running
Crystal
O ff
Running
Running
Running
Running
VCOs
O ff
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry.
Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-56 Power Management Requirements
SIGNAL
C P U _ S TO P #
P C I _ S TO P #
PD#
SIGNAL STATE
0 (Disabled)
2
1 (Enabled)
1
0 (Disabled)
2
1 (Enabled)
1
1 (Normal Operation)
3
0 (Power Down)
4
L a t e n cy
No. of rising edges of free running
PCICLK
1
1
1
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
3
ICS9248-56
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the
ICS9248-56.
The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the
ICS9248-56.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the
ICS9248-56.
It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the
ICS9248-56
internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
4
ICS9248-56
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the
ICS9248-56
prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
5
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