Integrated
Circuit
Systems, Inc.
ICS9250-30
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E and Solano type chipset
Output Features:
•
2 - CPUs @ 2.5V, up to 200MHz.
•
13 - SDRAM @ 3.3V, up to 200MHz.
•
3 - 3V66 @ 3.3V, 2x PCI MHz.
•
8 - PCI @3.3V.
•
1 - 48MHz, @3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
1 - REF @3.3V, 14.318MHz.
•
1 - IOAPIC @ 2.5V.
Features:
•
Support PC133 SDRAM.
•
Up to 200MHz frequency support
•
Support power management through PD#.
•
Spread spectrum for EMI control
(± 0.25% Center Spread or 0 to -0.5% down spread)
•
Uses external 14.318MHz crystal
•
FS pins for frequency select
Key Specifications:
•
CPU Output Jitter: <250ps
•
CPU Output Skew: <175ps
•
PCI Output Skew: <500ps
•
3V66 Output Skew <175ps
•
For group skew timing, please refer to the
Group Timing Relationship Table.
Pin Configuration
VDDREF
X1
X2
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1
*FS0/PCICLK0
1
*FS1/PCICLK1
1
*SEL24_48#/PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FS4*
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
1
24_48MHz/FS2 *
1
48MHz/FS3*
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
FS4 FS3 FS2 FS1 FS0 CPU SDRAM
0
0
0
0
0
66.67 100.00
0
0
0
1
1
68.33 102.50
0
0
1
1
0
80.00 120.00
0
0
1
1
1
83.00 124.50
0
1
0
0
0 100.00 100.00
0
1
0
1
1 103.00 103.00
0
1
1
1
0 115.00 115.00
0
1
1
1
1 200.00 200.00
1
0
0
0
0 133.33 133.33
1
0
0
0
1 166.67 166.67
1
0
0
1
1 137.00 137.00
1
0
1
1
1 160.00 160.00
1
1
0
0
0 133.33 100.00
1
1
0
0
1 166.67 125.00
1
1
0
1
1 137.00 102.75
1
1
1
1
1 160.00 120.00
3V66
66.67
68.33
80.00
83.00
66.67
68.67
76.67
66.67
66.67
83.34
68.50
80.00
66.67
83.34
68.50
80.00
PCI
33.33
34.17
40.00
41.50
33.33
34.33
38.33
33.33
33.33
41.67
34.25
40.00
33.33
41.67
34.25
40.00
REF0
CPU
DIVDER
2
CPUCLK [1:0]
SDRAM
DIVDER
12
SDRAM [11:0]
SDRAM_F
FS[4:0]
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
IOAPIC
PCI
DIVDER
8
PCICLK [7:0]
3V66
DIVDER
3
3V66 [2:0]
For other hardware/I
2
C selectable frequencies please
refer to Byte 0 frequency select register.
0398A—07/03/02
ICS9250-30
ICS9250-30
General Description
The
ICS9250-30
is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-
30 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN
PIN NAME
NUMBER
1, 9, 10, 18,
25, 32, 33, 37, VDD
45
2
3
4, 5, 14, 21,
28, 29, 36,
41, 49
8, 7, 6
11
12
20, 19, 17,
16, 15
13
SEL24_48#
22
23
24
34
35
PD#
SCLK
SDATA
48MHz
FS3
FS2
24_48MHz
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
PWR
OUT
PWR
OUT
IN
OUT
X1
X2
GND
3V66 [2:0]
PCICLK0
FS0
PCICLK1
FS1
PCICLK [7:3]
PCICLK2
TYPE
PWR
IN
OUT
PWR
OUT
OUT
IN
OUT
IN
OUT
OUT
3 . 3 V p ow e r s u p p l y
Cr ystal input, has inter nal load cap (33pF) and feedback
resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load
cap (33pF)
Ground pins for 3.3V supply
3.3V Fixed 66MHz clock outputs for HUB
3.3V PCI clock outputs
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V PCI clock outputs.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V PCI clock outputs.
3.3V PCI clock output.
Input logic select. When logic "0" is selected pin 35 = 48MHz
When logic "1" is selected pin 35 = 24MHz.
Asynchronous active low input pin used to power down the
device into a low power state. The inter nal clocks are disabled
and the VCO and the cr ystal are stopped. The latency of the
p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
Clock input of I
2
C serial input.
Data input for I
2
C serial input.
3.3V Fixed 48MHz clock output for USB.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V 24 or 48MHz output.
3.3V free r unning 100MHz SDRAM not affected by I
2
C
3.3V SDRAM output. All SDRAM outputs can be tur ned off
through I
2
C.
Ground for 2.5V power supply for CPU & APIC.
2.5V Host bus clock output. Output frequency der ived from FS
p i n s.
2.5V power suypply for CPU, IOAPIC.
2 . 5 V c l o ck o u t p u t s r u n n i n g a t 1 6 . 6 7 M H z .
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V, 14.318MHz reference clock output.
DESCRIPTION
38
SDRAM_F
48, 47, 46, 44,
43, 42, 40, 39, SDRAM [11:0]
31, 30, 27, 26
50
51, 52
53, 55
54
56
GNDL
CPUCLK [1:0]
VDDL
IOAPIC
FS4
REF0
0398A—07/03/02
2
ICS9250-30
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
Bit
Bit 2
Bit 7 Bit 6 Bit 5 Bit 4
CPUCLK
MHz
FS4
FS3 FS2 FS1 FS0
0
0
0
0
0
66.67
0
0
0
0
1
60.00
0
0
0
1
0
66.80
0
0
0
1
1
68.33
0
0
1
0
0
70.00
0
0
1
0
1
75.00
0
0
1
1
0
80.00
0
0
1
1
1
83.00
0
1
0
0
0
100.00
0
1
0
0
1
90.00
0
1
0
1
0
100.30
0
1
0
1
1
103.00
0
1
1
0
0
105.00
0
1
1
0
1
110.00
0
1
1
1
0
115.00
0
1
1
1
1
200.00
1
0
0
0
0
133.33
1
0
0
0
1
166.67
1
0
0
1
0
133.70
1
0
0
1
1
137.00
1
0
1
0
0
140.00
1
0
1
0
1
145.00
1
0
1
1
0
150.00
1
0
1
1
1
160.00
1
1
0
0
0
133.33
1
1
0
0
1
166.67
1
1
0
1
0
133.70
1
1
0
1
1
137.00
1
1
1
0
0
140.00
1
1
1
0
1
145.00
1
1
1
1
0
150.00
1
1
1
1
1
160.00
0-Frequency is selected by hardware select,
1- Frequency is selected by Bit 2,7:4
0- Normal
1- Spread spectrum enable
0- Running
1- Tristate all outputs
Description
SDRAM
MHz
3V66
MHz
PCICLK
33.33
30.00
33.40
34.17
35.00
37.50
40.00
41.50
33.33
30.00
33.43
34.33
35.00
36.67
38.33
33.33
33.33
41.67
33.43
34.25
35.00
36.25
37.50
40.00
33.33
41.67
33.43
34.25
35.00
36.25
37.50
40.00
IOAPIC
MHz
16.67
15.00
16.70
17.08
17.50
18.75
20.00
20.75
16.67
15.00
16.72
17.17
17.50
18.33
19.17
16.67
16.67
20.83
16.71
17.13
17.50
18.13
18.75
20.00
16.67
20.83
16.71
17.13
17.50
18.13
18.75
20.00
Spread Precentage
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
PWD
Bit
(2, 7:4)
Bit 3
Bit 1
Bit 0
100.00
66.67
90.00
60.00
100.20
66.80
102.50
68.33
105.00
70.00
112.50
75.00
120.00
80.00
124.50
83.00
100.00
66.67
90.00
60.00
100.30
66.87
103.00
68.67
105.00
70.00
110.00
73.33
115.00
76.67
200.00
66.67
133.33
66.67
166.67
83.34
133.70
66.85
137.00
68.50
140.00
70.00
145.00
72.50
150.00
75.00
160.00
80.00
100.00
66.67
125.00
83.34
100.28
66.85
102.75
68.50
105.00
70.00
108.75
72.50
112.50
75.00
120.00
80.00
latched inputs
00001
Note 1
0
1
0
Notes:
1.
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit
3.
2. The I
2
C readback for Bit 2, 7:4 indicate the revision code.
0398A—07/03/02
3
ICS9250-30
Byte 1: Control Register
(1 = enable, 0 = disable)
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
35
-
34
-
38
PWD
X
X
X
0
1
1
1
1
Description
FS3#
FS0#
FS2#
24_48MHz #
(Reserved)
48MHz
(Reserved)
SDRAM_F
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
39
40
42
43
44
46
47
48
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 3: Control Register
(1 = enable, 0 = disable)
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
20
19
17
16
15
13
12
11
PWD
1
1
1
1
1
1
1
1
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
8
6
7
-
54
-
51
52
PWD
1
1
1
X
1
X
1
1
Description
3V66_2
3V66_0
3V66_1
FS4#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Byte 5: Control Register
(1 = enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
26
27
30
31
PWD
1
1
1
X
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
24_48 MHz#
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
1
1
0
Description
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
0398A—07/03/02
4
ICS9250-30
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . .
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . .
4.6 V
3.6V
GND –0.5 V to V
DD
+0.5 V
0°C to +70°C
–65°C to +150°C
115°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters
T
A
= 0 - 70º C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX
V
DD
2
Input High Voltage
V
IH
+0.3
V
SS
Input Low Voltage
V
IL
0.8
-0.3
Input High Current
I
IH
V
IN
= V
DD
-5
5
V
IN
= 0 V; Inputs with no pull-up
-5
Input Low Current
I
IL1
resistors
V
IN
= 0 V; Inputs with pull-up
Input Low Current
I
IL2
-200
resistors
Cl = max cap loads; Select @
I
DD3.3OP
350
400
66MHz
Operating Supply Current
Cl = max cap loads; Select @
13
20
I
DDL2.5OP
66MHz
Cl = 0 pF; With Input to Vdd or
275
600
Power Down Current
I
DD3.3PD
Gnd
Input frequency
F
i
V
DD
= 3.3 V
14.32
7
Pin Inductance
L
pin
Logic Inputs
5
C
IN
1
Input Capacitance
Output pin capacitance
6
C
out
X1 & X2 pins
27
45
C
INX
T
Trans
To 1st crossing of target Freq.
3
Transition Time
1
From 1st crossing to 1% target
3
T
S
Settling Time
1
Freq.
From V
DD
= 3.3 V to 1% target
3
T
Stab
Clk Stabilization
1
Freq.
T
PZH,
T
PZL
output enable delay(all outputs)
1
10
Delay
1
output disable delay(all outputs)
1
10
T
PHZ,
T
PLZ
1
UNITS
V
V
µA
mA
µA
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
Guaranteed by design, not 100% tested in production.
0398A—07/03/02
5
微控制器 MCU
