Integrated
Circuit
Systems, Inc.
ICS9250-38
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK 408 clock for Almador-M mobile chipset with Tualatin
Pin Configuration
PIII processor.
VDDREF
1
56
REF
Output Features:
X1
2
55
FS1
•
3 Differential CPU Clock Pairs @ 3.3V
X2
3
54
FS0
GND
4
53
CPU_STOP#*
•
7 PCI (3.3V) @ 33.3MHz
PCICLK_F0
5
52
CPUCLKT0
PCICLK_F1
6
51
CPUCLKC0
•
3 PCI_F (3.3V) @ 33.3MHz
PCICLK_F2
7
50
VDDCPU
VDDPCI
8
49
CPUCLKT1
•
1 USB (3.3V) @ 48MHz
GND
9
48
CPUCLKC1
PCICLK0
10
47
GND
•
1 DOT (3.3V) @ 48MHz
PCICLK1
11
46
VDDCPU
PCICLK2
12
45
CPUCLKT2
•
1 REF (3.3V) @ 14.318MHz
PCICLK3
13
44
CPUCLKC2
•
1 3V66 (3.3V) @ 66.6MHz
VDDPCI
14
43
MULTSEL0*
GND
15
42
I REF
•
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
PCICLK4
16
41
GND
PCICLK5
17
40
FS2
•
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
PCICLK6
18
39
48MHz_USB
VDD3V66
19
38
48MHz_DOT
or 66.6MHz
GND
20
37
VDD48
•
1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
66MHz_OUT0/3V66_2
21
36
GND
66MHz_OUT1/3V66_3
22
35
3V66_1/VCH_CLK
Features:
66MHz_OUT2/3V66_4
23
34
PCI_STOP#*
66MHz_IN/3V66_5
24
33
3V66_0
•
Almador Chipset has a DLL driving the clock buffer
*PD#
25
32
VDD3V66
path for the 3 buffer path 66.6 MHz outputs,
VDDA
26
31
GND
GND
27
30
SCLK
66Buf(0:2).
Vtt_PWRGD#
28
29
SDATA
Almador board level designs MUST use pin 22,
66Buf_1, as the feedback connection from the
clock buffer path to the Almador (GMCH)
56-Pin 300mil SSOP/TSSOP
chipset.
* These inputs have 150K internal pull-up resistor to VDD.
•
Supports spread spectrum modulation,
down spread 0 to -0.5%.
•
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
66MHz Output Jitter (Buffered Mode Only) <100ps
Functionality
•
CPU Output Skew <100ps
Block Diagram
FS2
PLL2
48MHz_USB
48MHz_DOT
X1
X2
66MHz_IN
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
3
3
ICS9250-38
FS1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
66.66
100.00
200.00
133.33
66.66
100.00
200.00
133.33
Tristate
TCLK/2
3V66
(MHz)
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
Tristate
TCLK/4
66Buff[2:0]
3V66[4:2]
(MHz)
66.66
66.66
66.66
66.66
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
Tristate
TCLK/4
PCI_F
PCI
(MHz)
33.33
33.33
33.33
33.33
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
Tristate
TCLK/8
Reserved
Reserved
0
0
0
0
1
1
1
1
Mid
Mid
Mid
Mid
XTAL
OSC
3V66_1/VCH_CLK
REF
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:0)
PCICLK_F (2:0)
66MHz_OUT (2:0)
3V66 (5:2,0)
I REF
PCI
DIVDER
Stop
7
3
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Control
Logic
66MHz
DIVDER
3V66
DIVDER
3
5
Config.
Reg.
Reserved Reserved Reserved
Reserved Reserved Reserved
0404B—12/23/02
ICS9250-38
Pin Configuration
PIN NUMBER
1, 8, 14, 19, 26,
32, 37, 46, 50
2
3
7, 6, 5
4, 9, 15, 20, 27,
31, 36, 41, 47
18, 17, 16, 13,
12,11, 10
23, 22, 21
24
25
PIN NAME
VDD
X1
X2
TYPE
PWR
X2 Cr ystal Input
X1 Cr ystal
Output
3.3V power supply
DESCRIPTION
Cr ystal input,nominally 14.318MHz, with internal loading cap.
Cr ystal output, nominally 14.318MHz, with internal loading cap.
PCICLK_F (2:0)
GND
PCICLK (6:0)
66MHz_OUT (2:0)
3V66 (4:2)
66MHz_IN
3V66_5
PD#
OUT
PWR
OUT
OUT
OUT
IN
OUT
IN
Free running PCI clock not affected by PCI_STOP# for power
management as a function of the I
2
C stop control bits.
Ground pins for 3.3V supply
PCI clock outputs
66MHz buffered 66MHz_OUT from 66MHz_IN input.
66MHz reference clocks, from internal VCO
66MHz input to buffered 66MHz_OUT and PCI clocks
66MHz reference clock, from internal VCO
Invokes power-down mode. Active Low.
28
Vtt_PWRGD#
IN
I/O
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
OUT
This 3.3V LVTTL input is a level sensitive strobe used to determine
when FS[0:2] and MULTISEL0 inputs are valid and are ready to be
sampled
(active low)
Data pin for I
2
C circuitry 5V tolerant
Clock pin of I
2
C circuitry 5V tolerant
66MHz reference clocks, from internal VCO
Stops all PCICLKs at logic 0 level, when input low besides the PCICLK_F
clocks which are controllable by I2C bits whether they are free running or
stopped by PCI_STOP.
3.3V output selectable through
I
2
C
to be 66MHz from internal VCO or
48MHz (non-SSC)
48MHz output clock for DOT
48MHz output clock for USB
Special 3.3V input for Mode selection
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementor y" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
Stops all CPUCLKs at logic 0 level, when input low. The individual CPU clocks
are controllable by I2C bits whether they are free running or stopped by
CPU_STOP.
Frequency select pins
14.318MHz reference clock.
29
30
33
34
35
38
39
40
42
43
44, 48, 51
45, 49, 52
53
55, 54
56
SDATA
SCLK
3V66_0
PCI_STOP#
3V66_1/VCH_CLK
48MHz_DOT
48MHz_USB
FS2
I REF
MULTSEL0
CPUCLKC (2:0)
CPUCLKT (2:0)
CPU_STOP#
FS (1:0)
REF
Power Groups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR
0404B—12/23/02
(Digital)
VDDPCI
VDD3V66
VDDCPU
2
ICS9250-38
Truth Table
FS2
0
0
0
0
1
1
1
1
Mid
Mid
Mid
Mid
FS1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
66.66
100.00
200.00
133.33
66.66
100.00
200.00
133.33
Tristate
TCLK/2
3V66
(1:0)
(MHz)
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
Tristate
TCLK/4
66Buff (2:0)
3V66 (4:2)
(MHz)
66.66
66.66
66.66
66.66
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
Tristate
TCLK/4
Reser ved
Reser ved
66MHz_IN/
3V66_5
66.66
66.66
66.66
66.66
Input
Input
Input
Input
Tristate
TCLK/4
Reser ved
Reser ved
PCI_F
PCI
(MHz)
33.33
33.33
33.33
33.33
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
Tristate
TCLK/8
Reser ved
Reser ved
REF0
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Tristate
TCLK
Reser ved
Reser ved
USB/DOT
(MHz)
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
Tristate
TCLK/2
Reser ved
Reser ved
Reser ved Reser ved
Reser ved Reser ved
Maximum Allowed Current
Condition
Powerdown Mode
(PWRDWN# = 0)
Full Active
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
40mA
360mA
Host Swing Select Functions
MULTISEL0
Board Target
Trace/Term Z
50 ohms
50 ohms
Reference R,
Iref =
V
DD
/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Ioh = 4* I REF
Ioh = 6* I REF
Voh @ Z
0
1
1.0V @ 50
0.7V @ 50
0404B—12/23/02
3
ICS9250-38
Byte 0: Control Register
Bit
Bit 0
Bit 1
Bit 2
Pin#
54
55
40
Name
FS0
FS1
FS2
PWD
2
X
X
X
X
Bit 3
34
PCI_STOP#
3
1
Bit 4
Bit 5
Bit 6
Bit 7
53
35
-
-
CPU_STOP#
3V66_1/VCH
Spread Enabled
X
0
0
0
RW
R
RW
RW
Type
1
R
R
R
R
Description
Reflects the value of FS0 pin sampled on power up
Reflects the value of FS1 pin sampled on power up
Reflects the value of FS2 pin sampled on power up
Hardware mode: Reflects the value of PCI_STOP#
pin sampled on PWD
Software mode:
0=PCICLK stopped
1=PCICLK not stopped
Reflects the current value of the external
CPU_STOP# pin
VCH Select 66MHz/48MHz
0=66MHz, 1=48MHz
(Reser ved)
0=Spread Off, 1=Spread On
Byte 1: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
52, 51
49, 48
45, 44
52, 51
49, 48
45, 44
-
43
Name
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
-
MULTSEL0
PWD
2
1
1
1
0
0
0
0
X
Type
1
RW
RW
RW
RW
RW
RW
-
R
Description
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
0=Disabled 1=Enabled
4
4
Allow control of CPUCLKT0/C0 with asser tion of
CPU_STOP# 0=Not free running 1=Free running
Allow control of CPUCLKT1/C1 with asser tion of
CPU_STOP# 0=Not free running 1=Free running
Allow control of CPUCLKT2/C2 with asser tion of
CPU_STOP# 0=Not free running 1=Free running
(Reser ved)
Reflects the current value of MULTSEL0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I
2
C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2
C Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I
2
C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2
C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0404B—12/23/02
4
ICS9250-38
Byte 2: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD
2
1
1
1
1
1
1
1
0
Type
1
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
(Reser ved)
Byte 3: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
5
6
7
5
6
7
39
38
Name
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK_F0
PCICLK_F1
PCICLK_F2
48MHz_USB
48MHz_DOT
PWD
2
1
1
1
0
0
0
1
1
Type
1
RW
RW
RW
RW
RW
RW
RW
RW
Description
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
Allow control of PCICLK_F0 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F1 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F2 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
Byte 4: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
21
22
23
24
35
33
-
-
Name
3V66-2
3V66-3
3V66-4
3V66_5
3V66_1/VCH_CLK
3V66_0
-
-
PWD
2
1
1
1
1
1
1
0
0
Type
1
RW
RW
RW
RW
RW
RW
R
R
Description
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
0=Disabled 1=Enabled
4
(Reser ved)
(Reser ved)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0404B—12/23/02
5
