Integrated
Circuit
Systems, Inc.
ICS950902
Programmable Timing Control Hub™ for P4™
Recommended Application:
VIA P4X/P4M/KT/KN266/333 style chipsets.
Output Features:
•
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
1 - Pair of differential open drain CPU clocks (K7)
•
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
•
3 - AGP @ 3.3V
•
7 - PCI @ 3.3V (1 - Free running)
•
1 - 48MHz @ 3.3V fixed
•
1 - 24_48MHz @ 3.3V (Default 48MHz I
2
C select only)
•
2 - REF @ 3.3V, 14.318MHz
•
12 - SDRAM (6 pair - DDR) selectable
Key Specifications:
•
CPU_CS - CPUT/C: <±250ps
•
CPU_CS - AGP: <±250ps
•
CPU - DDR/SD: <±250ps
•
PCI - PCI: <500ps
•
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
DDR output buffer supports up to 200MHz.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I
2
C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
Frequency Table
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPUCLK
MHz
160.00
164.00
166.60
170.00
175.00
180.00
185.00
190.00
66.80
100.90
133.60
200.40
66.60
100.00
200.00
133.30
AGP
MHz
80.00
82.00
66.60
68.00
70.00
72.00
74.00
76.00
66.80
67.27
66.80
66.80
66.60
66.60
66.60
66.60
PCICLK
MHz
40.00
41.00
33.30
34.00
35.00
36.00
37.00
38.00
33.40
33.63
33.40
33.40
32.30
33.30
33.30
33.30
Pin Configuration
*FS0/REF0 1
GND 2
X1 3
X2 4
VDDAGP 5
*MODE/AGPCLK0 6
*SEL_408/K7/AGPCLK1 7
*(PCI_STOP#)AGPCLK2 8
GNDAGP 9
**FS1/PCICLK_F 10
**SEL_SDR/DDR#/PCICLK1 11
GNDPCI 13
PCICLK3 14
PCICLK4 15
VDDPCI 16
PCICLK5 17
*(CLK_STOP#)PCICLK6 18
GND48 19
*FS3/48MHz 20
*FS2/24_48MHz 21
AVDD48 22
VDD 23
GND 24
IREF 25
*(PD#)RESET# 26
SCLK 27
*MULTSEL/PCICLK2 12
56 Vtt_PWRGD#**/REF1
55 VDDREF
54 GND
53 CPUCLKT/CPUCLKODT
52 CPUCLKC/CPUCLKODC
51 VDDCPU3.3
50 VDDCPU2.5
49 CPUC_CS
48 CPUT_CS
47 GND
46 FBOUT
45 BUF_IN
44 DDRT0/SDRAM0
43 DDRC0/SDRAM1
42 DDRT1/SDRAM2
41 DDRC1/SDRAM3
40 VDD3.3_2.5
39 GND
38 DDRT2/SDRAM4
37 DDRC2/SDRAM5
36 DDRT3/SDRAM6
35 DDRC3/SDRAM7
34 VDD3.3_2.5
33 GND
32 DDRT4/SDRAM8
31 DDRC4/SDRAM9
30 DDRT5/SDRAM10
29 DDRC5/SDRAM11
MULTISEL0
Board Target
Trace/Term Z
50 ohms
50 ohms
Reference R,
Iref =
V
DD
/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Ioh = 4* I REF
Ioh = 6* I REF
Voh @ Z
SDATA 28
0
1
1.0V @ 50
0.7V @ 50
56-Pin 300-mil SSOP & 240-mil TSSOP
* Internal 120K pull-up resistor to VDD.
** Internal 120K pull-down resistor to GND.
0475G—03/23/04
ICS950902
Integrated
Circuit
Systems, Inc.
ICS950902
General Description
The
ICS950902
is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with
PC133 or DDR memory.
The
ICS950902
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
FBOUT
DDRC (5:0)/SDRAM (11,9,7,5,3,1)
DDRC (5:0)/SDRAM (10,8,6,4,2,0)
Power Groups
Pin Number
VDD
55
5
16
22
23
34, 40
50
51
0475G—03/23/04
GND
2
9
13
19
24
33, 39
47
54
Description
Xtal, Ref
AGP [0:2], CPU digital, CPU PLL
PCI [0:5], PCI_F outputs
48MHz, Fix Digital, Fix Analog
Master clock, CPU Analog
DDR/SDR outputs
2.5V CPUT/C_CS output
3.3V CPUT/C & CPUOD_T/C
2
Integrated
Circuit
Systems, Inc.
ICS950902
Pin Description
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN
NAME
*FS0/REF0
GND
X1
X2
VDDAGP
*MODE/AGPCLK0
*SEL_408/K7/AGPCLK1
*(PCI_STOP#)AGPCLK2
GNDAGP
**FS1/PCICLK_F
**SEL_SDR/DDR#/PCICLK1
*MULTSEL/PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
*(CLK_STOP#)PCICLK6
GND48
*FS3/48MHz
*FS2/24_48MHz
AVDD48
VDD
GND
IREF
PIN
TYPE
I/O
PWR
IN
OUT
PWR
I/O
I/O
I/O
PWR
I/O
I/O
I/O
PWR
OUT
OUT
PWR
OUT
I/O
PWR
I/O
I/O
PWR
PWR
PWR
OUT
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin.
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Power supply for AGP clocks, nominal 3.3V
Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / AGP clock output.
CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input
is activated by the MODE selection pin / AGP clock output.
Ground pin for the AGP outputs
Frequency select latch input pin / 3.3V PCI free running clock output.
Memory type select latch input pin 0= DDR, 1= PC133 SDRAM / 3.3V PCI clock output.
3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock output.
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
Stops all CPU, DDR/SDRAM and FB_OUT clocks at logic 0 level, when input low. This input
is activated by the MODE selection pin / PCI clock output.
Ground pin for the 48MHz outputs
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Power supply, nominal 3.3V
Ground pin.
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
Asynchronous active low input pin used to power down the device into a low power state.
This input is activated by the MODE selection pin / Real time system reset signal for
frequency gear ratio change or watchdog timer timeout. This signal is active low.
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
26
27
28
*(PD#)RESET#
SCLK
SDATA
I/O
IN
I/O
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive strength
Pin description continued on next page.
0475G—03/23/04
3
Integrated
Circuit
Systems, Inc.
ICS950902
Pin Description Continued
PIN
#
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PIN
NAME
DDRC5/SDRAM11
DDRT5/SDRAM10
DDRC4/SDRAM9
DDRT4/SDRAM8
GND
VDD3.3_2.5
DDRC3/SDRAM7
DDRT3/SDRAM6
DDRC2/SDRAM5
DDRT2/SDRAM4
GND
VDD3.3_2.5
DDRC1/SDRAM3
DDRT1/SDRAM2
DDRC0/SDRAM1
DDRT0/SDRAM0
BUF_IN
FBOUT
GND
CPUT_CS
CPUC_CS
VDDCPU2.5
VDDCPU3.3
CPUCLKC/CPUCLKODC
PIN
TYPE
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
OUT
PWR
OUT
OUT
PWR
PWR
OUT
DESCRIPTION
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Input Buffers for memory outputs.
Memory feed back output.
Ground pin.
"True" clocks of differential pair 2.5V push-pull CPU outputs.
Complementary" clocks of differential pair 2.5V push-pull CPU outputs.
Power pin for the CPUCLKs. 2.5V
Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "Complementary" clocks of differential pair
CPU outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias / "True" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up / 2.5V CPU clock output.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
valid and are ready to be sampled. This is an active low input. / 14.318 MHz reference clock.
53
54
55
56
CPUCLKT/CPUCLKODT
GND
VDDREF
Vtt_PWRGD#**/REF1
OUT
PWR
PWR
IN
Mode Pin - Power Management Input Control
MODE, Pin 6
(Latched Input)
0
1
Pin 26
PD#
(Input)
RESET#
(Output)
Pin 18
CLK_STOP#
(Input)
PCICLK6
(Output)
Pin 8
PCI_STOP#
(Input)
AGP2
(Output)
0475G—03/23/04
4
Integrated
Circuit
Systems, Inc.
ICS950902
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page
.
0475G—03/23/04
5
