DATASHEET
Eight Output Differential Buffer for PCI Express (50-200MHz)
Description
The 9DB801C is a DB800 Version 2.0 Yellow Cover part with
PCI Express support. It can be used in PC or embedded
systems to provide outputs that have low cycle-to-cycle jitter
(50ps), low output-to-output skew (100ps), and are PCI Express
gen 1 compliant. The 9DB801C supports a 1 to 8 output
configuration, taking a spread or non spread differential HCSL
input from a CK410(B) main clock such as 954101 and
932S401, or any other differential HCSL pair. 9DB801C can
generate HCSL or LVDS outputs from 50 to 200MHz in PLL
mode or 0 to 400Mhz in bypass mode. There are two de-jittering
modes available selectable through the HIGH_BW# input pin,
high bandwidth mode provides de-jittering for spread inputs and
low bandwidth mode provides extra de-jittering for non-spread
inputs. The SRC_STOP#, PD#, and individual OE# real-time
input pins provide completely programmable power
management control.
ICS9DB801C
Features/Benefits
•
•
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Supports polarity inversion to the output enables,
SRC_STOP and PD.
Key Specifications
•
•
•
•
•
•
•
•
Outputs cycle-cycle jitter < 50ps
Outputs skew: 50ps
50 - 200MHz operation
Extended frequency range in bypass mode to 400 MHz
PCI Express Gen I compliant
Real time PLL lock detect output pin
48-pin SSOP/TSSOP package
Available in RoHS compliant packaging
Output Features
•
•
•
8 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
Funtional Block Diagram
8
OE_(7:0)
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
STOP
LOGIC
8
DIF(7:0))
SRC_STOP#
HIGH_BW#
BYPASS#/PLL
PD#
SDATA
SCLK
CONTROL
LOGIC
IREF
LOCK
Note: Polarities shown for OE_INV = 0.
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9DB801C
REV C 08/16/07
1
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
Pin Configuration
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
LOCK
OE_7
OE_4
DIF_7
DIF_7#
OE_INV
VDD
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
HIGH_BW#
SRC_STOP#
PD#
GND
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE0#
OE3#
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE1#
OE2#
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
LOCK
OE7#
OE4#
DIF_7
DIF_7#
OE_INV
VDD
DIF_6
DIF_6#
OE6#
OE5#
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
HIGH_BW#
SRC_STOP
PD
GND
ICS9DB801
(Same as ICS9DB108)
OE_INV = 0
OE_INV = 1
Polarity Inversion Pin List Table
OE_INV
Pins
6
7
14
15
26
27
35
36
43
44
0
OE_0
OE_3
OE_1
OE_2
PD#
DIF_STOP#
OE_5
OE_6
OE_4
OE_7
1
OE0#
OE3#
OE1#
OE2#
PD
DIF_STOP
OE5#
OE6#
OE4#
OE7#
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9DB801
ICS9DB801C
REV C 08/16/07
2
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
Pin Description for OE_INV = 0
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
PIN TYPE
INPUT
POWER
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
INPUT
INPUT
I/O
DESCRIPTION
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9DB801C
REV C 08/16/07
3
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
Pin Description for OE_INV = 0
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PIN NAME
GND
PD#
SRC_STOP#
HIGH_BW#
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OE_5
OE_6
DIF_6#
DIF_6
VDD
OE_INV
DIF_7#
DIF_7
OE_4
OE_7
LOCK
PIN TYPE
POWER
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
POWER
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
DESCRIPTION
Ground pin.
Asynchronous active low input pin, with 120Kohm internal pull-
up resistor, used to power down the device. The internal clocks
are disabled and the VCO and the crystal are stopped.
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
46
47
48
IREF
GNDA
VDDA
INPUT
POWER
POWER
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9DB801C
REV C 08/16/07
4
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
Pin Description for OE_INV = 1
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE0#
OE3#
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE1#
OE2#
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
PIN TYPE
INPUT
POWER
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
INPUT
INPUT
I/O
DESCRIPTION
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9DB801C
REV C 08/16/07
5
