Integrated
Circuit
Systems, Inc.
ICSVF2510
3.3V Phase-Lock Loop Clock Driver
General Description
The ICSVF2510
is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The
ICSVF2510
operates at 3.3V
VCC and drives up to ten clock loads.
One bank of ten outputs provide low-skew, low-jitter
copies of CLKIN. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLKIN.
Outputs can be enabled or disabled via control (OE)
inputs. When the OE inputs are high, the outputs align in
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
The
ICSVF2510
does not require external RC filter
components. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost. The
test mode shuts off the PLL and connects the input
directly to the output buffer. This test mode, the
ICSVF2510
can be use as low skew fanout clock buffer device. The
ICSVF2510
comes in 24 pin 173mil Thin Shrink Small-
Outline package (TSSOP) package.
Features
•
•
•
•
•
•
•
•
•
Meets or exceeds PC133 registered DIMM
specification1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of ten outputs
Operating frequency 20MHz to 200MHz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
Industrial temperature version available
Block Diagram
FBOUT
CLK0
CLK1
CLK2
FBIN
CLKIN
PLL
CLK3
CLK4
AVCC
CLK5
CLK6
CLK7
CLK8
CLK9
OE
0722B—05/06/04
Pin Configuration
AGND
VCC
CLK0
CLK1
CLK2
GND
GND
CLK3
CLK4
VCC
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKIN
AVCC
VCC
CLK9
CLK8
GND
GND
CLK7
CLK6
CLK5
VCC
FBIN
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. Pitch
ICSVF2510
ICSVF2510
Pin Descriptions
PIN #
1
2, 10, 14
3
4
5
6, 7, 18, 19
8
9
11
12
13
15
16
17
20
21
22
23
24
PIN NAME
AGND
VCC
CLK0
CLK1
CLK2
GND
CLK3
CLK4
OE
1
FBOUT
FBIN
CLK5
CLK6
CLK7
CLK8
CLK9
VCC
AVCC
CLKIN
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
PWR
IN
IN
DESCRIPTION
Analog Ground
Power Supply (3.3V)
Buffered clock output.
Buffered clock output.
Buffered clock output.
Ground
Buffered clock output.
Buffered clock output.
Output enable (has internal pull_up). When high, normal operation.
When low, clock outputs are disabled to a logic low state.
Feedback output
Feedback input
Buffered clock output.
Buffered clock output.
Buffered clock output.
Buffered clock output.
Buffered clock output.
Power Supply (3.3V) digital supply.
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
Clock input
Note:
1. Weak pull-ups on these inputs
Functionality
INPUTS
OE
0
1
AVCC
3.33
3.33
CLK (9:0)
0
Driven
OUTPUTS
FBOUT
Driven
Driven
Source
PLL
PLL
PLL
Shutdown
N
N
Y
Y
0
0
CLKIN
1
0
CLKIN
Test mode:
When AVCC is 0, shuts off the PLL
and connects the input directly to the output buffers
Buffer Mode
0
Driven
Driven
Driven
0722B—05/06/04
2
ICSVF2510
Absolute Maximum Ratings
Supply Voltage (AVCC) . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
AVCC < (V
cc
+ 0.7 V)
4.3 V
GND –0.5 V to V
cc
+ 0.5 V
0°C to +70°C
–65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - OUTPUT
T
A
= 0 - 70°C; V
DD
= V
DDL
= 3.3 V +/-10%; C
L
= 30 pF; R
L
= 500 Ohms (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
I
OH
= -8 mA
Output High Voltage
V
OH
Output Low Voltage
V
OL
I
OL
= 8 mA
V
OH
= 2.4 V
Output High Current
I
OH
V
OH
= 2.0 V
V
OL
= 0.8 V
Output Low Current
I
OL
V
OL
= 0.55 V
1
Rise Time
T
r
V
OL
= 0.8 V, V
OH
= 2.0 V
Fall Time
1
1
MIN
2.4
TYP
2.9
0.25
27
39
26
19
1.1
1.1
50
MAX UNITS
V
0.4
V
mA
mA
2.1
2.7
52
75
100
100
ns
ns
%
ps
ps
ps
ps
ns
0.5
0.5
48
T
f
V
OH
= 2.0 V, V
OL
= 0.8 V
D
t
V
T
= 1.5 V;C
L
=30 pF
Cycle to Cycle jitter
1
T
CYC
- T
CYC
at 66-100 MHz ; loaded outputs
Absolute Jitter
1
T
JABS
10000 cycles; C
L
= 30 pF
Skew
1
T
sk
V
T
= 1.5 V (Window) Output to Output
Phase error
Delay Input-Output
1
1
1
Duty Cycle
T
pe
D
R1
V
T
= Vdd/2; CLKIN-FBIN
V
T
= 1.5 V; PLL_EN = 0
-75
3.3
75
3.7
Guaranteed by design, not 100% tested in production.
0722B—05/06/04
3
ICSVF2510
Electrical Characteristics - Input & Supply
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-10% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating current
Input Capacitance
1
SYMBOL
CONDITIONS
V
IH
V
IL
I
IH
V
IN
= V
DD
I
IL
V
IN
= 0 V;
I
DD1
C
IN1
C
L
= 0 pF; F
IN
@ 66MHz
Logic Inputs
MIN
2
V
SS
- 0.3
TYP
0.1
19
4
MAX
UNITS
V
DD
+ 0.3
V
0.8
V
100
uA
50
uA
170
mA
pF
Guaranteed by design, not 100% tested in production.
Timing requirements over recommended ranges of supply
voltage and operating free-air temperature
Symbol
F
OP
F
CLK
Parameter
Test Conditions
Operating frequency
Min.
20
Max.
200
Unit
MHz
Input clock
25
200
MHz
frequency
Input clock
frequency duty
40
60
%
cycle
Stabilization time
After power up
15
µs
Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal.
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK.
Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not applicable.
0722B—05/06/04
4
ICSVF2510
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
500
Ω
Figure 1. Load Circuit for Outputs
Notes:
Figure 2. Voltage Waveforms
1. C
L
includes probe and jig capacitance.
Propagation Delay Times
2. All input pulses are supplied by generators having the following
characteristics:
PRR
≤
133 MHz, Z
O
= 5 0
Ω,
T
r
≤
1.2 ns, T
f
≤
1.2 ns.
3. The outputs are measured one at a time with one transition per measurement.
Figure 3. Phase Error and Skew Calculations
0722B—05/06/04
5
