80C86
March 1997
CMOS 16-Bit Microprocessor
Description
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, minimum for
small systems and maximum for larger applications such as
multiprocessing, allow user configuration to achieve the
highest performance level. Full TTL compatibility (with the
exception of CLOCK) and industry standard operation allow
use of existing NMOS 8086 hardware and software designs.
Features
• Compatible with NMOS 8086
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low Power Operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary, or Decimal
- Multiply and Divide
• Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
[ /Title
(80C86
)
/Sub-
ject
(CMO
S 16-
Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Inter-
sil
Corpo-
ration,
16 Bit
uP,
micro-
proces-
sor,
8086,
PC)
/Cre-
Ordering Information
PACKAGE
PDIP
TEMP. RANGE
0
o
C to +70
o
C
0
o
C to +70
o
C
0
o
C
+70
o
C
+85
o
C
5MHz
CP80C86
8MHz
PKG.
NO.
CP80C86-2 E40.6
IP80C86-2
E40.6
-40
o
C to +85
o
C lP80C86
PLCC
CS80C86
-40
o
C to +85
o
C lS80C86
CERDIP
to
CD80C86
ID80C86
-40
o
C
CS80C86-2 N44.65
IS80C86-2
N44.65
CD80C86-2 F40.6
ID80C86-2
F40.6
F40.6
to
-55
o
C to +125
o
C MD80C86/B MD80C86-
2/B
SMD#
CLCC
SMD#
-55
o
C to +125
o
C MR80C86/B MR80C86-
2/B
-55
o
C to +125
o
C 8405201QA 8405202QA F40.6
J44.A
-55
o
C to +125
o
C 8405201XA 8405202XA J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2957.1
3-141
80C86
Pinouts
80C86 (DIP)
TOP VIEW
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MAX
40 V
CC
39 AD15
38 A16/S3
37 A17/S4
36 A18/S5
35 A19/S6
34 BHE/S7
33 MN/MX
32 RD
31 RQ/GT0
30 RQ/GT1
29 LOCK
28 S2
27 S1
26 S0
25 QS0
24 QS1
23 TEST
22 READY
21 RESET
(HOLD)
(HLDA)
(WR)
(M/IO)
(DT/R))
(DEN)
(ALE)
(INTA)
(MIN)
80C86 (PLCC, CLCC)
TOP VIEW
A16/S3
A16/S3
A17/S4
A18/S5
A17/S4
A18/S5
39
38
AD11
AD12
AD13
AD14
MAX MODE
80C86
AD11
AD12
AD13
AD14
MIN MODE
80C86
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1 44 43 42 41 40
AD15
GND
V
CC
NC
AD15
GND
V
CC
NC
NC
A19/S6
NC
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
37
BHE/S7
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
MN/MX
RD
HOLD
HLDA
WR
M/IO
DT/R
DEN
READY
RESET
TEST
INTR
INTA
GND
CLK
ALE
NMI
NC
NC
MIN MODE
80C86
MAX MODE
80C86
READY
RESET
TEST
INTR
GND
CLK
3-142
QS1
QS0
NMI
NC
NC
80C86
Functional Diagram
EXECUTION UNIT
REGISTER FILE
DATA POINTER
AND
INDEX REGS
(8 WORDS)
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
16-BIT ALU
FLAGS
BUS INTERFACE UNIT
4
16
3
4
BHE/S7
A19/S6
A16/S3
AD15-AD0
INTA, RD, WR
DT/R, DEN, ALE, M/IO
6-BYTE
INSTRUCTION
QUEUE
TEST
INTR
NMI
RQ/GT0, 1
HOLD
HLDA
3
RESET READY MN/MX GND
V
CC
2
CONTROL AND TIMING
LOCK
2
3
QS0, QS1
S2, S1, S0
CLK
MEMORY INTERFACE
C-BUS
B-BUS
ES
BUS
INTERFACE
UNIT
CS
SS
DS
IP
INSTRUCTION
STREAM BYTE
QUEUE
EXECUTION UNIT
CONTROL SYSTEM
A-BUS
AH
BH
CH
EXECUTION
UNIT
DH
SP
BP
SI
DI
AL
BL
CL
DL
ARITHMETIC/
LOGIC UNIT
FLAGS
3-143
80C86
Pin Description
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
PIN
NUMBER
2-16, 39
SYMBOL
AD15-AD0
TYPE
I/O
DESCRIPTION
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and
data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-
D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory
or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-
dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-
ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”
or “grant sequence”.
ADDRESS/STATUS: During T1, these are the four most significant address lines for memory op-
erations. During I/O operations these lines are LOW. During memory and I/O operations, status
information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of
the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3
are encoded as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold ac-
knowledge” or “grant sequence”.
S4
0
0
1
1
S3
0
1
0
1
CHARACTERISTICS
Alternate Data
Stack
Code or None
Data
A19/S6
A18/S5
A17/S4
A16/S3
35-38
O
BHE/S7
34
O
BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to
enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices
tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE
is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-
ferred on the high portion of the bus. The S7 status information is available during T2, T3 and
T4. The signal is active LOW, and is held at high impedance to the last valid logic level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during
T1 for the first interrupt acknowledge cycle.
BHE
0
0
1
1
A0
0
1
0
1
CHARACTERISTICS
Whole Word
Upper Byte From/to Odd Address
Lower Byte From/to Even address
None
RD
32
O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-
pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on
the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-
teed to remain HIGH in T2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-
quence”.
READY: is the acknowledgment from the addressed memory or I/O device that will complete the
data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gener-
ator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.
Correct operation is not guaranteed if the Setup and Hold Times are not met.
READY
22
I
3-144
80C86
Pin Description
(Continued)
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
PIN
NUMBER
18
SYMBOL
INTR
TYPE
I
DESCRIPTION
INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle
of each instruction to determine if the processor should enter into an interrupt acknowledge op-
eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-
ory. It can be internally masked by software resetting the interrupt enable bit.
lNTR is internally synchronized. This signal is active HIGH.
TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.
NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is
not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the
end of the current instruction. This input is internally synchronized.
RESET: causes the processor to immediately terminate its present activity. The signal must tran-
sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,
as described in the Instruction Set description, when RESET returns LOW. RESET is internally
synchronized.
CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a
33% duty cycle to provide optimized internal timing.
VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for de-
coupling.
GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is rec-
ommended for decoupling.
TEST
23
I
NMI
17
I
RESET
21
I
CLK
19
I
VCC
40
GND
1, 20
MN/MX
33
I
MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
Minimum Mode System
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V
CC
). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
PIN
NUMBER
28
SYMBOL
M/IO
TYPE
O
DESCRIPTION
STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-
ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains
valid until the final T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic
one during local bus “hold acknowledge”.
WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending
on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active
LOW, and is held to high impedance logic one during local bus “hold acknowledge”.
INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is
active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never
floated.
ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the
82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.
Note that ALE is never floated.
WR
29
O
INTA
24
O
ALE
25
O
3-145
