IDT49FCT5805/A/B/C
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
FEATURES:
−
−
−
−
−
−
10 CMOS outputs
Monitor output
Rail-to-rail output voltage swing
Input hysteresis for better noise margin
Monitor output
Guaranteed low skew:
•
0.3ns output skew
•
0.6ns opposite transition
•
1ns different devices
Std., A, B, and C speed grades
Available in QSOP and SOIC packages
IDT49FCT5805/A/B/C
ADVANCE
INFORMATION
DESCRIPTION
The 49FCT5805 clock buffer/driver circuits can be used for clock
buffering schemes where low skew is a key parameter. This device offers
two banks of five non-inverting outputs. The 49FCT5805 device provides
low propagation delay buffering with on-chip skew of 0.3ns for same-
transition, same-bank signals.
The 49FCT5805 is characterized for operation at -40°C to +85°C.
−
−
FUNCTIONAL BLOCK DIAGRAM
OE A
5
IN A
OA 5
OA 1
MON
5
IN B
OB 5
OB 1
OE B
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
MARCH 2000
DSC-4579/-
IDT49FCT5805/A/B/C
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
V
C CA
OA1
OA2
OA3
G ND
A
OA4
OA5
G NDQ
OEA
INA
1
2
3
4
5
6
7
8
9
10
20
19
18
17
SO20-2 16
SO20-8 15
14
13
12
11
V
C CB
O B1
O B2
O B3
G ND
B
O B4
O B5
MON
O EB
INB
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM(2)
V
TERM(3)
V
AC
I
OUT
P
MAX
T
STG
Description
Supply Voltage to Ground
DC Output Voltage V
OUT
DC Input Voltage V
IN
AC Input Voltage (pulse width
≤20ns)
DC Output Current V
IN
< 0
DC Output Current Max. Sink Current/Pin
Maximum Power
Dissipation (T
A
= 85°C)
Storage Temperature
QSOP
SOIC
(1)
Unit
V
V
V
V
mA
mA
W
W
°C
Max.
– 0.5 to +7
– 0.5 to +7
– 0.5 to +7
-3
-20
120
.82
.75
– 65 to +150
QSOP/ SOIC
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE
QSOP
Pins
C
IN
Typ.
4
(T
A
= +25
O
C, f = 1.0MHz, V
IN
= 0V)
SOIC
Typ.
5
Max.
(1)
6
Unit
pF
Max.
(1)
6
NOTE:
1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names
OEA, OEB
INA, INB
OAn, OBn
MON
I/O
I
I
O
O
Description
Output Enable Inputs
Clock Inputs
Clock Outputs
Monitor Outputs (non-disable)
2
IDT49FCT5805/A/B/C
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%, V
HC
= V
CC
- 0.2V, V
LC
= 0.2V
Symbol
V
IH
V
IL
V
IC
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Clamp Diode Voltage
(3)
Output HIGH Voltage
Test Conditions
Guaranteed Logic HIGH for All Inputs
Guaranteed Logic LOW for All Inputs
Vcc = Min., I
IN
= -18mA
Vcc = Min., V
IN
= V
IH
or V
IL
, I
OH
= -300µA
Vcc = Min., V
IN
= V
IH
or V
IL
, I
OH
= -15mA
Vcc = Min., V
IN
= V
IH
or V
IL
, I
OH
= -24mA
V
OL
I
IN
I
OZ
I
OFF
I
OS
∆V
T
Output LOW Voltage
Input Leakage Current
Output Leakage Current
I/O Power Off Leakage
Short Circuit Current
Input Hysteresis
(2,3)
Min.
2
—
—
V
HC
3.6
2.4
—
—
—
—
—
Typ.
(1)
—
—
–0.7
Vcc
4.3
3.8
GND
0.3
—
—
—
—
0.2
Max.
—
0.8
–1.2
—
—
—
V
LC
0.55
±1
±1
±1
—
—
Unit
V
V
V
V
V
µA
µA
µA
mA
V
Vcc = Min., V
IN
= V
IH
or V
IL
, I
OL
= 300µA
Vcc = Min., V
IN
= V
IH
or V
IL
, I
OL
= 64mA
Vcc = Max., V
IN
= Vcc or GND
Vcc = Max., V
OUT
= Vcc or GND
Vcc = 0V, V
IN
or V
O
≤
4.5V
Vcc = Max., V
OUT
= GND
V
TLH
- V
THL
for All Inputs
–
60
—
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CC
∆I
CC
I
CCD
I
C
Parameter
Quiescent Power Supply Current
Supply Current per Input HIGH
Dynamic Power Supply Current per Output
(2)
Total Supply Current Examples
(2,4)
Test Conditions
(1)
V
CC
= Max., V
IN
= GND or Vcc
V
CC
= Max., V
IN
= 3.4V
V
CC
= Max.,
OEA
=
OEB
= GND
Outputs Enabled, 50% duty cycle
V
CC
= Max.,
OEA
=
OEB
= GND
50% duty cycle, f
I
= 10MHz
Five outputs toggling
V
CC
= Max.,
OEA
=
OEB
= GND
50% duty cycle, f
I
= 2.5MHz
All outputs toggling
Typ.
(3)
0.005
0.5
0.1
V
IN
= GND or Vcc
V
IN
= GND or 3.4V
V
IN
= GND or Vcc
V
IN
= GND or 3.4V
3
5
Max.
0.5
2.5
0.2
Unit
mA
mA
mA/MHz
mA
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Guaranteed by design but not tested. C
L
= 0pF.
3. Typical values are for reference only. Conditions are V
CC
= 5.0V, T
A
= 25°C.
4. I
C
= I
CC
+ (∆I
CC
)(D
H
)(N
T
) + I
CCD
(f
O
)(N
O
)
where:
D
H
= Input Duty Cycle
N
T
= Number of TTL HIGH inputs at D
H
f
O
= Output Frequency
N
O
= Number of outputs at f
O
3
IDT49FCT5805/A/B/C
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SKEW CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%
C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
49FCT5805
Symbol
t
SK(01)
t
SK(02)
t
SK(P)
t
SK(T)
Parameter
(1)
Skew between all outputs, same transition, same bank
Skew between outputs of all banks, same transition
Pulse Skew; skew between opposite transitions of the same
output (t
PHL
- t
PLH
)
Part-to-part skew
(2)
Min.
—
—
—
—
Max.
0.5
0.7
1
1.5
49FCT5805/A
Min.
—
—
—
—
Max.
0.35
0.7
1
1.5
49FCT5805/B
Min.
—
—
—
—
Max.
0.3
0.5
0.8
1.2
49FCT5805/C
Min.
—
—
—
—
Max.
0.3
0.4
0.6
1
Unit
ns
ns
ns
ns
NOTES:
1. Skew parameters are guaranteed across temperature range, but not tested. Skew parameters are measured at 0.5Vcc.
2. t
SK(T)
only applies to devices of the same transition, part type, temperature, power supply voltage, loading, package, and speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%
C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
49FCT5805
Symbol
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PZH
t
R
t
F
Parameter
(1)
Propagation Delay
(2)
INA to OAn, INB to OBn
Output Enable Time
Output Disable Time
(3)
Output Rise Time, 0.8V to 2V
(3)
Output Fall Time, 2Vcc to 0.8Vcc
(3)
Min.
1.5
1.5
1.5
—
—
Max.
5.6
8
7
1.5
3
49FCT5805/A
Min.
1.5
1.5
1.5
—
—
Max.
5.3
8
7
1.5
3
49FCT5805/B
Min.
1.5
1.5
1.5
—
—
Max.
5
7
6
1.5
3
49FCT5805/C
Min.
1.5
1.5
1.5
—
—
Max.
4.5
7
6
1.5
3
Unit
ns
ns
ns
ns
ns
NOTES:
1. Minimums guaranteed but not production tested. Timing parameters are measured at 0.5Vcc.
2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation
delays do not imply limit skew.
3. This parameter is guaranteed but not production tested.
4
IDT49FCT5805/A/B/C
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
Parameter
Tested
Switch
Position
t
PLZ
, t
PZL
All Others
V
CC
V
IN
Pulse
Generator
50
Ω
DUT
50pF
450
Ω
V
OUT
500
Ω
Closed
Open
7.0 V
50
Ω
coax to
oscilloscope
Pulse generator for all pulses: f
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
3V
INPUT
t
PLH
t
PHL
V
OH
2.0V
0.5Vcc
0.8V
V
OL
t
R
t
F
t
PLH
OUPUT
t
PHL
V
OH
0.5Vcc
V
OL
t
SK(p)
= t
PHL
- t
PLH
1.5V
0V
INPUT
3V
1.5V
0V
OUPUT
PROPAGATION DELAY
PULSE SKEW — t
SK(P)
3V
3V
INPUT
t
PLHA
V
OH
t
PHLA
V
OH
OUPUT A
0.5Vcc
V
OL
t
SK(02)
OUPUT B
t
SK(02)
V
OH
0.5Vcc
V
OL
t
PLHB
t
PHLB
1.5V
0V
INPUT
t
PLH1
t
PHL1
1.5V
0V
OUPUT 1
0.5Vcc
V
OL
t
SK(01)
t
SK(01)
V
OH
0.5Vcc
V
OL
t
PLH2
t
PHL2
t
SK(01)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
OUPUT 2
t
SK(02)
= t
PLHB
- t
PLHA
or t
PHLB
- t
PHLA
OUTPUT SKEW (SAME BANK) — t
SK(O1)
OUPUT SKEW (DIFFERENT BANKS) — t
SK(O2)
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
t
PZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
DISABLE
3V
1.5V
0V
t
PLZ
3V
1.5V
0.3V V
OL
t
PHZ
0.3V V
OH
PART 2 OUTPUT
t
SK(t)
t
SK(t)
PART 1 OUTPUT
INPUT
t
PLH1
t
PHL1
V
OH
0.5Vcc
V
OL
V
OH
0.5Vcc
V
OL
0V
t
PLH2
t
PHL2
3V
1.5V
0V
t
SK(t)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
ENABLE AND DISABLE TIMES
5
PART-TO-PART SKEW — t
SK(T)
