®
CMOS STATIC RAM
64K (16K x 4-BIT)
with Output Control
IDT6198S
IDT6198L
Integrated Device Technology, Inc.
FEATURES:
• High-speed (equal access and cycle times)
— Military: 20/25/35/45/55/70/85ns (max.)
— Commercial: 15/20/25/35ns (max.)
• Output Enable (
OE
) pin available for added system flexibility
• Low-power consumption
• JEDEC compatible pinout
• Battery back-up operation—2V data retention (L version
only)
• 24-pin CERDIP, high-density 28-pin leadless chip carrier,
and 24-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT6198 is a 65,536-bit high-speed static RAM orga-
nized as 16K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability technology—CMOS. This state-of-the-
art technology, combined with innovative circuit design tech-
niques, provides a cost-effective approach for memory inten-
sive applications. Timing parameters have been specified to
meet the speed demands of the IDT79R3000 RISC proces-
sors.
Access times as fast as 15ns are available. The IDT6198
offers a reduced power standby mode, I
SB1
, which is activated
when
CS
goes HIGH. This capability significantly decreases
system, while enhancing system reliability. The low-power
version (L) also offers a battery backup data retention capa-
bility where the circuit typically consumes only 30µW when
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply.
The IDT6198 is packaged in either a 24-pin 300 mil CERDIP,
28-pin leadless chip carrier or 24-pin J-bend small outline IC.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
GND
65,536-BIT
MEMORY ARRAY
DECODER
A
13
I/O
0
I/O
1
I/O
2
I/O
3
COLUMN I/O
INPUT
DATA
CONTROL
CS
WE
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2987 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994
Integrated Device Technology, Inc.
MAY 1994
6.3
DSC-1010/4
1
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TRUTH TABLE
(1)
V
CC
A
13
A
12
A
11
A
10
A
9
NC
I/O
3
I/O
2
I/O
1
I/O
0
Mode
Standby
Read
Write
Read
CS
H
L
L
L
WE
X
H
L
H
OE
X
L
X
H
I/O
High-Z
DATA
OUT
DATA
IN
High-Z
Power
Standby
Active
Active
Active
2987 tbl 02
D24-1
&
SO24-4
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't Care
GND
CS
OE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Com’l.
Mil.
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output
Current
0 to +70
–55 to +125
–55 to +125
1.0
50
WE
2987 drw 02
DIP/SOJ
TOP VIEW
T
A
A
0
NC
NC
V
CC
NC
INDEX
–55 to +125
–65 to +135
–65 to +150
1.0
50
°C
°C
°C
W
mA
T
BIAS
T
STG
P
T
I
OUT
3
2
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CS
4
5
6
7
8
9
10
11
1
28 27
26
25
24
23
L28-2
22
21
20
19
18
12
13 14 15 16 17
NC
A
13
A
12
A
11
A
10
A
9
I/O
3
I/O
2
I/O
1
2987 drw 03
OE
GND
NC
WE
I/O
0
NOTE:
2987 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
LCC
TOP VIEW
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
7
7
Unit
pF
pF
PIN DESCRIPTIONS
Name
A
0
–A
13
Description
Address Inputs
Chip Select
Write Enable
Output Enable
Data Input/Output
Power
Ground
2987 tbl 01
C
I/O
NOTE:
2987 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
CS
WE
OE
I/O
0
–
I/O
3
V
CC
GND
6.3
2
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Max. Unit
5.5
0
6.0
0.8
V
V
V
V
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5V
±
10%
5V
±
10%
2987 tbl 06
Typ.
5.0
0
—
—
NOTE:
2987 tbl 05
1. V
IL
(min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT6198S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Condition
V
CC
= Max.,
V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH,
V
OUT
= GND to V
CC
I
OL
= 10mA, V
CC
= Min.
I
OL
= 8mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= –4mA, V
CC
= Min.
—
2.4
MIL.
COM’L.
MIL.
COM’L.
Min.
—
—
—
—
Max.
10
5
10
5
0.5
0.4
—
IDT6198L
Min.
—
—
—
—
—
—
2.4
Max.
5
2
5
2
0.5
0.4
—
V
2987 tbl 07
Unit
µA
µA
V
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
6198S15
6198L15
Symbol
I
CC1
Parameter
Operating Power
Supply Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f = 0
(2)
Dynamic Operating
Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f = f
MAX(2)
Standby Power Supply
Current (TTL Level)
CS
≥
V
IH
, V
CC
= Max.,
Outputs Open, f = f
MAX(2)
Full Standby Power
Supply Current (CMOS
Level)
CS
≥
V
HC
,
V
CC
=Max., V
IN
≥
V
HC
or
V
IN
≤
V
LC
, f = 0
(2)
6198S20
6198L20
6198S25
6198L25
Mil.
6198S35
6198L35
6198S45
6198L45
Mil.
6198S55/70/85
6198L55/70/85
Com’l.
Mil.
Power
Com’l. Mil. Com’l. Mil. Com’l.
S
L
S
L
S
L
S
L
100
75
135
125
60
45
20
1.5
—
—
—
—
—
—
—
—
100
70
130
115
55
40
15
0.5
105
80
160
130
70
50
25
1.5
100
70
125
105
50
35
15
0.5
Com’l. Mil. Com’l.
Unit
mA
105
80
155
120
60
40
20
1.5
100
70
125
105
45
30
15
0.5
105
80
140
115
50
35
20
1.5
—
—
—
—
—
—
—
—
105
80
140
110
50
35
20
1.5
—
—
—
—
—
—
—
—
105
80
140
110
50
35
20
1.5
I
CC2
mA
I
SB
mA
I
SB1
mA
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX
address and data inputs are cycling at the maximum frequency of read cycles of 1/t
RC
. f = 0 means no input lines change.
2987 tbl 06
6.3
3
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) V
LC
= 0.2V, V
HC
= V
CC
- 0.2V
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR(3)
t
R(3)
|I
LI
|
(3)
Max.
V
CC
@
2.0V
—
600
150
—
—
2
3.0V
—
900
225
—
—
2
Unit
V
µA
ns
ns
µA
2987 tbl 09
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Input Leakage Current
Test Condition
—
MIL.
COM’L.
Min.
2.0
—
—
0
t
RC(2)
—
2.0v
—
10
10
—
—
—
3.0V
—
15
15
—
—
—
CS
≥
V
HC
V
IN
≥
V
HC
or
≤
V
LC
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
LOW V
CC
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
V
CC
4.5V
t
CDR
V
DR
≥2V
4.5V
t
R
V
IH
V
DR
2987 drw 04
CS
V
IH
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2987 tbl 10
5V
480
Ω
DATA
OUT
255
Ω
30pF*
5V
480Ω
DATA
OUT
255Ω
5pF*
2987 drw 05
2987 drw 06
Figure 1. AC Test Load
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for t
OLZ
, t
CLZ
, t
OHZ
, t
WHZ
, t
CHZ
and t
OW
)
6.3
4
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
6198S15
(1)
6198L15
(1)
6198S20
6198L20
6198S25
6198L25
6198S35
6198L35
6198S45/55
(2)
6198S70/85
(2)
6198L45/55
(2)
6198L70/85
(2)
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ(3)
t
OE
t
OLZ(3)
t
CHZ(3)
t
OHZ(3)
t
OH
t
PU(3)
t
PD(3)
Parameter
Min. Max. Min. Max. Min.
Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
15
—
—
5
—
5
2
2
5
0
—
—
15
15
—
8
—
7
7
—
—
15
20
—
—
5
—
5
2
2
5
0
—
—
19
20
—
9
—
8
8
—
—
20
25
—
—
5
—
5
2
2
2
0
—
—
25
25
—
11
—
10
9
—
—
25
35
—
—
5
—
5
2
2
5
0
—
—
35
35
—
18
—
14
15
—
—
35
45/55
—
—
5
—
5
—
—
5
0
—
—
45/55
45/55
—
25/35
—
15/20
15/20
—
—
45/55
70/85
—
—
5
—
5
—
—
5
0
—
—
70/85
70/85
—
45/55
—
25/30
25/30
—
—
70/85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed by device characterization but is not production tested.
2987 tbl 11
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
t
OH
OE
t
OE
CS
t
CLZ
DATA
OUT
t
OLZ (5)
t
ACS
(5)
t
OHZ (5)
t
CHZ (5)
DATA VALID
2987 drw 07
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state voltage.
6.3
5
