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HIGH-SPEED 64K x 18

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

Features

◆

IDT709389L

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 7.5/9/12ns (max.)

– Industrial: 9ns (max.)

Low-power operation

– IDT709389L

Active: 1.2W (typ.)

Standby: 2.5mW (typ.)

Flow-Through or Pipelined output mode on either Port via

the

FT/PIPE

pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 12ns cycle time, 83MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

Available in a 100-pin Thin Quad Flatpack (TQFP) package

Functional Block Diagram

0/1

/PIPE

0/1

1b 0b

b a

1a 0a

0a 1a

0b 1b

0/1

/PIPE

I/O

-I/O

17L

I/O

-I/O

I/O

Control

I/O

-I/O

17R

I/O

Control

I/O

-I/O

15L

CLK

Counter/

Address

Reg.

MEMORY

ARRAY

Counter/

Address

Reg.

15R

CLK

ADS

CNTEN

CNTRST

ADS

CNTEN

CNTRST

4844 drw 01

JANUARY 2009

DSC-4844/5

IDT709389L

High-Speed 64K x 18 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT709389 is a high-speed 64K x 18 bit synchronous Dual-

Port RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneous access of any address from both ports. Registers on

control, data, and address inputs provide minimal setup and hold

times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times.

With an input data register, the IDT709389 has been optimized for

applications having unidirectional or bidirectional data flow in bursts.

An automatic power down feature, controlled by

and CE

permits

the on-chip circuitry of each port to enter a very low standby power

mode. Fabricated using IDT’s CMOS high-performance technology,

these devices typically operate on only 1.2W of power.

Pin Configurations

(1,2,3)

INDEX

CNTEN

CLK

ADS

GND

ADS

CLK

CNTEN

11/07/01

10L

11L

12L

13L

14L

15L

CNTRST

R/W

Vcc

FT/PIPE

I/O

17L

I/O

16L

GND

I/O

15L

I/O

14L

I/O

13L

I/O

12L

I/O

11L

I/O

10L

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

709389PF

PN100-1

(4)

100-Pin TQFP

Top View

(5)

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

10R

11R

12R

13R

14R

15R

CNTRST

R/W

GND

FT/PIPE

I/O

17R

GND

I/O

16R

I/O

15R

I/O

14R

I/O

13R

I/O

12R

I/O

11R

4844 drw 02

NOTES:

1. All V

pins must be connected to power supply.

2. All GND pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

I/O

Vcc

I/O

GND

I/O1

I/O

GND

I/O

Vcc

I/O

10R

6.42

IDT709389L

High-Speed 64K x 18 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

, CE

R/W

- A

15L

I/O

- I/O

17L

CLK

ADS

CNTEN

CNTRST

FT/PIPE

Right Port

, CE

R/W

- A

15R

I/O

- I/O

17R

CLK

ADS

CNTEN

CNTRST

FT/PIPE

GND

Names

Chip Enables

Read/Write Enable

Output Enable

Address

Data Input/Output

Clock

Upper Byte Select

Lower Byte Select

Address Strobe

Counter Enable

Counter Reset

Flow-Through/Pipeline

Power

Ground

4844 tbl 01

Truth Table I—Read/Write and Enable Control

(1,2,3)

CLK

↑

R/W

Upper

Byte

I/O

9-17

High-Z

DATA

High-Z

DATA

OUT

High-Z

DATA

OUT

High-Z

Lower B

yte

I/O

0-8

High-Z

DATA

High-Z

DATA

OUT

DATA

OUT

High-Z

Mode

Deselected—Power Down

Both Bytes Deselected

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

Outputs Disabled

4844 tbl 02

NOTES:

1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, CNTRST

= X.

is an asynchronous input signal.

6.42

IDT709389L

High-Speed 64K x 18 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table II—Address Counter Control

(1,2,6)

Address

Addr

Used

Ap + 1

CLK

↑

ADS

(4)

CNTEN

(5)

CNTRST

I/O

(3)

I/O

(0)

I/O

(n)

I/O

(p)

I/O

(p+1)

Mode

Counter Reset to Address 0

External Address Utilized

External Address Blocked—Counter Disabled (Ap reused)

Counter Enable—Internal Address Generation

4844 tbl 03

NOTES:

1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

LB, UB,

and

= V

; CE

and R/W = V

3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.

ADS

is independent of all other signals including

, CE

and

LB.

5. The address counter advances if

CNTEN

= V

on the rising edge of CLK, regardless of all other signals including

, CE

and

LB.

6. While an external address is being loaded (ADS = V

), R/W = V

is recommended to ensure data is not written arbitrarily.

Recommended Operating

Recommended DC Operating

Temperature and Supply Voltage Conditions

Grade

Commercial

Industrial

Ambient

Temperature

(2)

C to +70

-40

C to +85

GND

Vcc

5.0V

10%

5.0V

10%

4844 tbl 04

Symbol

GND

Parameter

Supply Voltage

Ground

Input High Voltage

Input Low Voltage

Min.

4.5

2.2

-0.5

(2)

Typ.

5.0

____

Max.

5.5

6.0

(1)

0.8

Unit

4844 tbl 05

NOTES:

1. This is the parameter T

. This is the "instant on" case temperature.

____

NOTES:

1. V

TERM

must not exceed V

+ 10%.

2. V

> -1.5V for pulse width less than 10ns.

Absolute Maximum Ratings

(1)

Symbol

TERM

(2)

Rating

Terminal Voltage

with Respect

to GND

Temperature

Under Bias

Storage

Temperature

DC Output

Current

Commercial

& Industrial

-0.5 to +7.0

Unit

Capacitance

(1)

Symbol

OUT

(3)

= +25°C, f = 1.0MH

)

Parameter

Input Capacitance

Output Capacitance

Conditions

(2)

= 3dV

OUT

= 3dV

Max.

Unit

4844 tbl 07

BIAS

STG

OUT

-55 to +125

-65 to +150

4844 tbl 06

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch from

0V to 3V or from 3V to 0V.

3. C

OUT

also references C

I/O

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed V

+ 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> V

+ 10%.

6.42

IDT709389L

High-Speed 64K x 18 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature Supply Voltage Range

= 5.0V ± 10%)

709389L

Symbol

Parameter

Input Leakage Current

(1)

Output Leakage Current

Output Low Voltage

Output High Voltage

Test Conditions

= 5.5V, V

= 0V to V

= V

or CE

= V

, V

OUT

= 0V to V

= +4mA

= -4mA

Min.

___

Max.

0.4

___

Unit

µA

4844 tbl 08

___

2.4

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(3)

= 5V ± 10%)

709389L7

Com'l Only

Symbol

Parameter

Dynamic Operating

Current

(Both Ports Active)

Standby Current

(Both Ports - TTL

Level Inputs)

Standby Current

(One Port - TTL

Level Inputs)

Full Standby Current

(Both Ports -

CMOS Level Inputs)

Full Standby Current

(One Port -

CMOS Level Inputs)

Test Condition

and

= V

Outputs Disabled

f = f

MAX

(1)

= V

f = f

MAX

(1)

"A"

= V

and

"B"

= V

(3)

Active Port Outputs

Disabled, f=f

MAX

(1)

Both Ports CE

and

> V

- 0.2V

> V

- 0.2V or

< 0.2V, f = 0

(2)

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

> V

- 0.2V or

< 0.2V, Active Port

Outp uts Disabled , f = f

MAX

(1)

Version

COM'L

IND

COM'L

IND

COM'L

IND

COM'L

IND

COM'L

IND

Typ.

(4)

275

____

709389L9

Com'l

& Ind

Typ.

(4)

250

300

175

195

0.5

170

190

Max.

400

430

135

160

275

295

3.0

6.0

270

290

709389L12

Com'l Only

Typ.

(4)

230

____

Max.

465

____

Max.

355

____

Unit

SB1

____

150

____

110

____

SB2

200

____

295

____

150

____

240

____

SB3

0.5

____

3.0

____

0.5

____

3.0

____

SB4

190

____

290

____

140

____

225

____

NOTES:

1. At f = f

MAX

, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t

CYC

, using "AC TEST CONDITIONS" at input levels of

GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. I

CC DC

(f=0) = 150mA (Typ).

5. CE

= V

means

= V

and CE

= V

means

= V

or CE

= V

< 0.2V means

< 0.2V and CE

> V

- 0.2V

> V

- 0.2V means

> V

- 0.2V or CE

< 0.2V

"X" represents "L" for left port or "R" for right port.

4844 tbl 09

6.42

参数对比

与IDT709389L9PF相近的元器件有：IDT709389L7PF8、IDT709389L9PFI8、IDT709389L9PFI、IDT709389L9PF8、IDT709389L12PF、IDT709389L12PF8、IDT709389L7PF。描述及对比如下：

型号	IDT709389L9PF	IDT709389L7PF8	IDT709389L9PFI8	IDT709389L9PFI	IDT709389L9PF8	IDT709389L12PF	IDT709389L12PF8	IDT709389L7PF
描述	Dual-Port SRAM, 64KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 64KX18, 18ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 64KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 64KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 64KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 64KX18, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 64KX18, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 64KX18, 18ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	QFP	QFP	QFP	QFP	QFP	QFP	QFP	QFP
包装说明	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
针数	100	100	100	100	100	100	100	100
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	20 ns	18 ns	20 ns	20 ns	20 ns	25 ns	25 ns	18 ns
其他特性	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	66 MHz	83 MHz	66 MHz	66 MHz	66 MHz	50 MHz	50 MHz	83 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0
长度	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
内存密度	1179648 bit	1179648 bit	1179648 bit	1179648 bit	1179648 bit	1179648 bit	1179648 bit	1179648 bit
内存集成电路类型	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
内存宽度	18	18	18	18	18	18	18	18
湿度敏感等级	3	3	3	3	3	3	3	3
功能数量	1	1	1	1	1	1	1	1
端口数量	2	2	2	2	2	2	2	2
端子数量	100	100	100	100	100	100	100	100
字数	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words
字数代码	64000	64000	64000	64000	64000	64000	64000	64000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	85 °C	85 °C	70 °C	70 °C	70 °C	70 °C
组织	64KX18	64KX18	64KX18	64KX18	64KX18	64KX18	64KX18	64KX18
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP
封装等效代码	QFP100,.63SQ,20	QFP100,.63SQ,20	QFP100,.63SQ,20	QFP100,.63SQ,20	QFP100,.63SQ,20	QFP100,.63SQ,20	QFP100,.63SQ,20	QFP100,.63SQ,20
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	240	240	240	240	240	240	240	240
电源	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
最大待机电流	0.003 A	0.003 A	0.009 A	0.009 A	0.003 A	0.003 A	0.003 A	0.003 A
最小待机电流	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
最大压摆率	0.4 mA	0.465 mA	0.43 mA	0.43 mA	0.4 mA	0.355 mA	0.355 mA	0.465 mA
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
处于峰值回流温度下的最长时间	20	20	20	20	20	20	20	20
宽度	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Base Number Matches	1	1	1	1	1	1	1	-