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IDT70P246L55BYI

SRAM

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厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
厂商名称
IDT (Integrated Device Technology)
包装说明
,
Reach Compliance Code
unknown
Base Number Matches
1
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VERY LOW POWER 1.8V
8K/4K x 16 DUAL-PORT
STATIC RAM
Features
PRELIMINARY
IDT70P256/246L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Industrial: 55ns (max.)
Low-power operation
IDT70P256/246L
Active: 27mW (typ.)
Standby: 3.6
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
Supports 3.0V and 2.5V I/O's
Input Read Register
Output Drive Register
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 1.8V (±100mV) power supply
Available in 100 Ball 0.5mm-pitch BGA
Industrial temperature range (-40°C to +85°C)
Green parts available, see ordering information
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
L
(2)
,
I/O
8R
-I/O
15R
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
Address
Decoder
(2)
A
12L
(1)
A
0L
Address
Decoder
MEMORY
ARRAY
A
12R
(1)
A
0R
CE
L
OE
L
R/W
L
IRR
0
,IRR
1
INPUT
READ REGISTER
AND
OUTPUT
DRIVE REGISTER
SFEN
13
13
CE
R
OE
R
R/W
R
OD R
0
-
ODR
4
CE
L
OE
L
R/W
L
SEM
L
INT
L
(2)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(2)
5699 drw 01
NOTES:
1. A
12X
is a NC for IDT70P246.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
JULY 2008
1
©2008 Integrated Device Technology, Inc.
DSC-5699/1
IDT70P256/246L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Preliminary
Industrial Temperature Range
Description
The IDT70P256/246 is a very low power 8K/4K x 16 Dual-Port
Static RAM. This device provides two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic power
down feature controlled by
CE
permits the on-chip circuitry of each port
to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 27mW of power.
The IDT70P256/246 is packaged in a 100 ball 0.5mm- pitch Ball
Grid Array. The package is a 1mm thick and designed to fit in wireless
handset applications.
Pin Configurations
(2,3,4)
70P256/246BY
BY-100
08/03/07
100-Ball 0.5mm Pitch BGA
Top View
(5)
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1
A
5R
B1
A
8R
B2
A
11R
B3
UB
R
B4
Vss
B5
SEM
R
I/O
15R
I/O
12R
I/O
10R
B6
B7
B8
B9
Vss
B10
A
3R
C1
A
4R
C2
A
7R
C3
A
9R
C4
CE
R
C5
R/W
R
C6
OE
R
V
DDQR
I/O
9R
C7
C8
C9
I/O
6R
C10
A
0R
D1
A
1R
D2
A
2R
D3
A
6R
D4
LB
R
D5
IRR
1
D6
I/O
14R
I/O
11R
I/O
7R
D7
D8
D9
Vss
D10
ODR
4
ODR
2
BUSY
R
INT
R
E1
E2
E3
E4
A
10R
E5
A
12R
(1)
E6
I/O
13R
I/O
8R
E7
E8
I/O
5R
E9
I/O
2R
E10
Vss
F1
V
DD
F2
ODR
3
F3
INT
L
F4
Vss
F5
Vss
F6
I/O
4R
V
DDQR
I/O
1R
F7
F8
F9
Vss
F10
SFEN
ODR
1
BUSY
L
G1
G2
G3
A
1L
G4
V
DD
G5
Vss
G6
I/O
3R
G7
I/O
0R
I/O
15L
V
DDQL
G8
G9
G10
ODR
0
H1
A
2L
H2
A
5L
H3
A
12L
(1)
H4
OE
L
H5
I/O
3L
I/O
11L
I/O
12L
I/O
14L
I/O
13L
H6
H7
H8
H9
H10
,
A
0L
J1
A
4L
J2
A
9L
J3
LB
L
J4
CE
L
J5
I/O
1L
V
DDQL
J6
J7
NC
J8
NC
J9
I/O
10L
J10
A
3L
K1
A
7L
K2
A
10L
K3
IRR
0
K4
V
DD
K5
Vss
K6
I/O
4L
K7
I/O
6L
K8
I/O
8L
K9
I/O
9L
K10
A
6L
A
8L
A
11L
UB
L
SEM
L
R/W
L
I/O
0L
I/O
2L
I/O
5L
I/O
7L
5699 drw 02c
NOTES:
1. A
12X
is a NC for IDT70P246.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70P256/246L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
IDT70P256/246L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Preliminary
Industrial Temperature Range
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
12L
(1)
I/O
0L
- I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
12R
(1)
I/O
0R
- I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
IRR
0
, IRR
1
ODR
0
- ODR
4
SFEN
(2)
V
DD
V
DDQL
V
DDQR
V
SS
Right Port
Names
Chip Enable (Input)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Semaphore Enable (Input)
Upper Byte Select (Input)
Lower Byte Select (Input)
Interrupt Flag (Output)
Busy Flag (Output)
Input Read Register (Input)
Output Drive Register (Output)
Special Function Enable (Input)
Power (1.8V) (Input)
Left Port I/O Supply Voltage
(3.0V) (Input)
Right Port I/O Supply Voltage
(3.0V) (Input)
Ground (0V) (Input)
5699 tbl 01
NOTE:
1. A
12X
is a NC for IDT70P246.
2.
SFEN
is active when either
CE
L
= V
IL
or
CE
R
= V
IL
.
SFEN
is inactive when
CE
L
=
CE
R
= V
IH
.
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
X
L
L
L
L
L
L
X
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
Outputs
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected: Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
5699 tbl 02
NOTE:
1. A
0L
— A
12L
A
0R
— A
12R
6.42
3
IDT70P256/246L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Preliminary
Industrial Temperature Range
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
X
H
X
L
L
R/W
H
H
X
X
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
8-15
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Outputs
I/O
0-7
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write D
IN0
into Semaphore Flag
Write D
IN0
into Semaphore Flag
Not Allowed
Not Allowed
5699 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all of the I/O's (I/O
0
-I/O
15
). These eight semaphores are addressed by A
0
-A
2
.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
V
TERM
V
TERM
(2)
T
BIAS
(3)
T
STG
T
JN
I
OUT
(for
V
DDQx
= 3.0V)
Rating
Supply Voltage on V
DD
with Respect to GND
Supply Voltage on V
DDQL
with Respect to GND
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +2.9
-0.5 to +3.6
-0.5 to V
DD
+0.3
-55 to +125
-65 to +150
+150
20
Unit
V
V
V
o
C
C
C
o
o
mA
5699 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V for more than 25% of the cycle time or 10ns maximum, and
is limited to < 20mA for the period over V
TERM
= V
DD
+ 0.3V
.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
6.42
4
IDT70P256/246L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
IDT70P256/246L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Preliminary
Industrial Temperature Range
Capacitance
Symbol
C
IN
C
OUT
(TA = +25°C, f = 1.0MHz)
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
11
Unit
pF
pF
5699 tbl 07
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Industrial
Ambient
Temperature
-40
O
C to +85
O
C
GND
0V
V
DD
1.8V
+
100mV
5699 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
Recommended DC Operating Conditions
(V
DDQX
= 3.0V±300mV)
Symbol
V
DD
V
DDQX
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Port Supply Voltage
Ground
Input High Voltage (V
DDQX
= 3.0V)
Input Low Voltage (V
DDQX
= 3.0V)
Min.
1.7
2.7
0
2.0
-0.2
Typ.
1.8
3.0
0
___
Max.
1.9
3.3
0
V
DDQX
+ 0.2
0.6
Unit
V
V
V
V
V
5699tbl 06
___
Recommended DC Operating Conditions
(V
DDQX
= 2.5V±100mV)
Symbol
V
DD
V
DDQX
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Port Supply Voltage
Ground
Input High Voltage (V
DDQX
= 2.5V)
Input Low Voltage (V
DDQX
= 2.5V)
Min.
1.7
2.4
0
1.7
-0.3
Typ.
1.8
2.5
0
___
Max.
1.9
2.6
0
V
DDQX
+ 0.3
0.7
Unit
V
V
V
V
V
5699 tbl 06_5
___
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
DD
+ 0.3V.
3.
SFEN
operates at the 1.8V V
IH
and V
IL
voltage levels.
6.42
5
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参数对比
与IDT70P246L55BYI相近的元器件有:70P246L55BYI、702020.920.25LF、IDT70P246L55BYGI8、IDT70P246L55BYI8、IDT70P256L55BYGI8。描述及对比如下:
型号 IDT70P246L55BYI 70P246L55BYI 702020.920.25LF IDT70P246L55BYGI8 IDT70P246L55BYI8 IDT70P256L55BYGI8
描述 SRAM SRAM Fixed Resistor, Wire Wound, 0.5W, 0.92ohm, 300V, 0.25% +/-Tol, -2,2ppm/Cel, SRAM SRAM SRAM
Reach Compliance Code unknown unknown compliant unknown unknown unknown
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) - IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Base Number Matches 1 1 - 1 1 -
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