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Features

◆

HIGH-SPEED 2.5V

256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

PRELIMINARY

IDT70T651/9S

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T651/9 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

◆

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad

Flatpack and 208-ball fine pitch Ball Grid Array.

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

BBBB

EEEE

3210

R RRR

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_L Dout18-26_R

Dout27-35_L Dout27-35_R

256/128K x 36

MEMORY

ARRAY

I/O

0L-

I/O

35L

Di n_L

Di n_R

I/O

0R -

I/O

35R

17L(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

17R(1)

R/W

BUSY

L (2,3)

SEM

INT

L(3)

(4)

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

TDI

TD O

JTAG

TC K

TMS

TRST

M/S

BUSY

R(2,3)

SEM

INT

R(3)

(4)

NOTES:

1. Address A

17x

is a NC for IDT70T659.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,

INTx,

M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

CONTROL

LOGIC

4869 drw 01

NOVEMBER 2003

DSC-5632/3

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous

Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a

stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS-

TER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the

IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider

memory system applications results in full-speed, error-free operation

without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

Description

feature controlled by the chip enables (either

or CE

) permit the

on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T651/9 has a RapidWrite Mode which allows the designer

to perform back-to-back write operations without pulsing the R/W input

each cycle. This is especially significant at the 8 and 10ns cycle times of

the IDT70T651/9, easing design considerations at these high perfor-

mance levels.

The 70T651/9 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controlled by the OPT pins. The power supply for

the core of the device (V

) is at 2.5V.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3)

70T651/9BC

BC-256

(5,6)

256-Pin BGA

Top View

A10

A11

A12

A13

A14

A15

A16

03/18/03

TDI

17L(4)

14L

11L

B10

INT

B11

B12

B13

B14

B15

B16

I/O

18L

TDO

15L

12L

R/W

C10

C11

C12

C13

C14

I/O

17L

C15

C16

I/O

18R

I/O

19L

16L

13L

10L

SEM

BUSY

D10

D11

D12

D13

OPT

I/O

17R

I/O

16L

D14

D15

D16

I/O

20R

I/O

19R

I/O

20L

DDQL

DDQR

DDQL

DDQR

I/O

15R

I/O

15L

I/O

16R

E10

E11

E12

E13

E14

E15

E16

I/O

21R

I/O

21L

I/O

22L

DDQL

F10

F11

DDQR

I/O

13L

I/O

14L

I/O

14R

F12

F13

F14

F15

F16

I/O

23L

I/O

22R

I/O

23R

DDQL

G10

G11

DDQR

I/O

12R

I/O

13R

I/O

12L

G12

G13

G14

G15

G16

I/O

24R

I/O

24L

I/O

25L

DDQR

H10

H11

H12

DDQL

I/O

10L

I/O

11L

I/O

11R

H13

H14

H15

H16

I/O

26L

I/O

25R

I/O

26R

DDQR

J10

J11

J12

DDQL

I/O

J13

J14

I/O

10R

J15

J16

I/O

27L

I/O

28R

I/O

27R

DDQL

K10

K11

DDQR

I/O

K12

K13

K14

K15

K16

I/O

29R

I/O

29L

I/O

28L

DDQL

L10

L11

L12

DDQR

I/O

L13

L14

L15

L16

I/O

30L

I/O

31R

I/O

30R

DDQR

M10

M11

M12

DDQL

I/O

M13

M14

I/O

M15

M16

I/O

32R

I/O

32L

I/O

31L

DDQR

N10

N11

DDQL

I/O

N12

N13

N14

N15

N16

I/O

33L

I/O

34R

I/O

33R

DDQR

DDQL

DDQR

DDQL

P10

P11

P12

P13

I/O

P14

I/O

P15

P16

I/O

35R

I/O

34L

TMS

16R

13R

10R

SEM

BUSY

R10

R11

R12

R13

I/O

R14

R15

I/O

R16

I/O

35L

TRST

15R

12R

R/W

T10

M/S

T11

T12

T13

OPT

T14

T15

T16

TCK

17R(4)

14R

11R

INT

5632 drw 02f

NOTES:

1. All V

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. A

17X

is a NC for IDT70T659.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

DDQR

I/O

18R

I/O

18L

TDI

TDO

17L(4)

16L

15L

14L

13L

12L

11L

10L

SEM

R/W

BUSY

INT

OPT

I/O

17L

I/O

17R

DDQR

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

03/18/03

100

101

102

103

104

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

70T651/9DR

DR-208

(5,6,7)

208-Pin

PQFP

Top View

(8)

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

5632 drw 02d

NOTES:

1. All V

pins must be connected to 2.5V power supply.

All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V) and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground.

4. A

17X

is a NC for IDT70T659.

5. Package body is approximately 28mm x 28mm x 3.5mm.

6. This package code is used to reference the package diagram.

7. 8ns Commercial and 10ns Industrial speed grades are not available in the DR-208 package.

8. This text does not indicate orientation of the actual part-marking.

DDQL

I/O

35R

I/O

35L

TMS

TCK

TRST

17R(4)

16R

15R

14R

13R

12R

11R

10R

SEM

R/W

BUSY

INT

M/S

OPT

I/O

DDQL

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

03/18/03

I/O

19L

I/O

18L

TDO

16L

12L

10 11

D D

INT

13 14

OPT

16 17

I/O

17L

SEM

I/O

20R

I/O

18R

TDI

17L (4)

13L

9 L

BUSY

DD QR

I/O16L I/O

15R

DD QL

I/O

19R

DD QR

14 L

1 0L

I/O

16R

I/O

15L

I/O

22L

I/O

21L

I/O

20L

15L

11L

7 L

D D

I/O

17R

D DQ L

I/O

14L

I/O

14R

I/O

23L

I/O

22R

D DQ R

I/O

21R

I/O

12L

I/O

13R

I/O

13L

DD QL

I/O

23R

I/O

24L

I/O

12R

I/O

11L

DD QR

I/O

26L

I/O

25L

I/O

24R

I/O

DD QL

I/O

10L

I/O

11R

I/O

26R

DD QR

I/O

25R

70T651/9BF

BF-208

(5,6)

208-Ball

fpBGA

Top View

(7)

D D

I/O

10R

DD QL

D D

DD QR

I/O

28R

I/O

27R

S S

I/O

D DQL

I/O8R

I/O

29R

I/O

28L

D DQ R

I/O

27L

I/O

DD QL

I/O

29L

I/O

30R

I/O

DD QR

I/O

31L

I/O

31R

I/O

30L

I/O

DD QL

I/O

32R

I/O

32L

D DQ R

I/O

3 5R

TRST

16R

12R

SEM

INT

I/O

33L

I/O

34R

TCK

17R(4)

13R

BUSY

5 R

D DQ L

I/O

DD QR

I/O

33R

I/O

34L

DD QL

TMS

14R

1 0R

S S

I/O

35L

D D

15R

11R

7 R

OPT

I/O

5632 drw 02e

NOTES:

1. All V

pins must be connected to 2.5V power supply.

All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V) and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground.

4. A

is a NC for IDT70T659.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.