HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
IDT70V35/34S/L
IDT70V25/24S/L
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70V35/34
– Commercial: 15/20/25ns (max.)
– Industrial: 20ns
IDT70V25/24
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns
Low-power operation
– IDT70V35/34S
– IDT70V35/34L
Active: 430mW (typ.)
Active: 415mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660
µ
W (typ.)
– IDT70V25/24S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V25/24L
Active: 380mW (typ.)
Standby: 660
µ
W (typ.)
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
Control
I/O
0L
-I/O
8L
(4)
BUSY
L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
Address
Decoder
13
A
12L
(1)
A
0L
MEMORY
ARRAY
13
Address
Decoder
A
12R
(1)
A
0R
CE
L
OE
L
R/W
L
SEM
L
INT
L
(3)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5624 drw 01
M/S
NOTES:
1. A
12
is a NC for IDT70V34 and for IDT70V24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70V25/24.
5. I/O
8
x - I/O
15
x for IDT70V25/24.
OCTOBER 2008
1
DSC-5624/7
©2008 Integrated Device Technology, Inc.
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V35/34 (IDT70V25/24) is a high-speed 8/4K x 18 (8/4K
x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is de-
signed to be used as a stand-alone Dual-Port RAM or as a combination
MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 430mW (IDT70V35/34) and 400mW
(IDT70V25/24) of power.
The IDT70V35/34 (IDT70V25/24) is packaged in a plastic 100-pin
Thin Quad Flatpack. The IDT70V25/24 is packaged in a ceramic 84-pin
PGA and 84-Pin PLCC.
Pin Configurations
(1,2,3,4)
06/24/04
Index
N/C
N/C
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
Vss
I/O
15L
I/O
16L
V
DD
Vss
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
N/C
N/C
100 99 98 9796 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
74
73
72
71
70
69
68
67
66
I/O
10L
I/O
9L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
Vss
I/O
1L
I/O
0L
OE
L
V
DD
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
12L
(1)
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
IDT70V35/34PF
PN100-1
(5)
100-Pin TQFP
Top View
(6)
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
Vss
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
,
5624 drw 02
NOTES:
1. A
12
is a NC for IDT70V34.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
I/O
7R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
Vss
I/O
16R
OE
R
R/W
R
Vss
SEM
R
CE
R
UB
R
LB
R
A
12R
(1)
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
6.42
2
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3,4)
(con't)
Index
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
V
SS
I/O
14L
I/O
15L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
SS
I/O
1L
I/O
0L
OE
L
V
DD
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
12L
(1)
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
06/24/04
IDT70V25/24PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
V
SS
I/O
15R
OE
R
R/W
R
V
SS
SEM
R
CE
R
UB
R
LB
R
A
12R
(1)
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
NOTES:
1. A
12
is a NC for IDT70V24.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
5624 drw 03
6.42
3
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3,4)
(con't)
06/11/04
63
61
60
58
55
54
51
48
46
45
42
11
I/O
7L
66
I/O
5L
64
I/O
4L
62
I/O
2L
59
I/O
0L
56
OE
L
49
SEM
L
50
LB
L
47
A
11L
44
A
10L
43
A
7L
40
10
I/O
10L
67
I/O
8L
65
I/O
6L
I/O
3L
I/O
1L
57
UB
L
53
CE
L
52
A
12L(1)
A
9L
A
8L
41
A
5L
39
09
I/O
11L
69
I/O
9L
68
V
SS
V
DD
R/W
L
A
6L
38
A
4L
37
08
I/O
13L
72
I/O
12L
71
73
33
A
3L
35
A
2L
34
07
I/O
15L
75
I/O
14L
70
V
DD
74
BUSY
L
IDT70V25/24
G
G84-3
(4)
84-Pin PGA
Top View
(5)
32
A
0L
31
INT
L
36
06
I/O
0R
76
V
SS
77
V
SS
78
V
SS
28
M/S
29
A
1L
30
05
I/O
1R
79
I/O
2R
80
V
DD
A
0R
INT
R
26
BUSY
R
27
04
I/O
3R
81
I/O
4R
83
7
11
12
A
2R
23
A
1R
25
03
I/O
5R
82
1
I/O
7R
2
5
8
V
SS
V
SS
10
SEM
R
14
17
20
A
5R
22
A
3R
24
02
I/O
6R
84
3
I/O
9R
I/O
10R
4
I/O
13R
6
I/O
15R
9
R/W
R
15
UB
R
13
A
11R
16
A
8R
18
A
6R
19
A
4R
21
01
I/O
8R
A
I/O
11R
B
I/O
12R
C
I/O
14R
D
OE
R
E
LB
R
F
CE
R
G
A
12R(1)
H
A
10R
J
A
9R
K
A
7R
L
5624 drw 04
Index
NOTES:
1. A
12
is a NC for IDT70V24.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. G84-3 package body is approximately 1.12 in x 1.12 in x .16 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
4
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3,4)
(con't)
I/O
3L
I/O
2L
I/O
1L
I/O
0L
R/W
L
I/O
5L
I/O
7L
I/O
6L
I/O
4L
OE
L
V
SS
V
DD
UB
L
LB
L
A
10L
CE
L
06/08/04
A
12L(1)
A
11L
SEM
L
A
9L
INDEX
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
V
SS
I/O
14L
I/O
15L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
73
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IDT70V25/24J
J84-1
(4)
84-Pin PLCC
Top View
(5)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
,
55
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
A
12R(1)
I/O
12R
I/O
15R
A
11R
V
SS
CE
R
I/O
9R
A
10R
A
9R
A
8R
R/W
R
V
SS
SEM
R
I/O
13R
UB
R
I/O
10R
I/O
11R
I/O
14R
NOTES:
1. A
12
is a NC for IDT70V24.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
OE
R
6.42
5
LB
R
A
7R
5624 drw 05
DSP 与 ARM 处理器
