HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
Features:
◆
◆
IDT70V27S/L
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/35ns (max.)
Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for bus
matching capability
Dual chip enables allow for depth expansion without
external logic
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 100-pin Thin Quad Flatpack (TQFP), and 144-
pin Fine Pitch BGA (fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/W
R
UB
R
CE
0R
CE
1L
OE
L
LB
L
CE
1R
OE
R
LB
R
I/O
8-15L
I/O
0-7L
BUSY
L
(1,2)
I/O
8-15R
I/O
Control
I/O
Control
I/O
0-7R
BUSY
R
(1,2)
,
A
14L
A
0L
Address
Decoder
A
14L
A
0L
CE
0L
32Kx16
MEMORY
ARRAY
70V27
Address
Decoder
A
14R
A
0R
CE
1L
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
14R
A
0R
CE
0R
CE
1R
OE
R
R/
W
L
SEM
L
INT
L
(2)
(2)
R/
W
R
SEM
R
(2)
INT
R
3603 drw 01
M/
S
NOTES:
1)
BUSY
is an input as a Slave (M/S=V
IL
) and an output as a Master (M/S=V
IH
).
2)
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
SEPTEMBER 2006
6.01
1
©2006 Integrated Device Technology, Inc.
DSC 3603/10
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Description:
The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (
CE
0
and
CE
1
) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 500mW of power. The IDT70V27
is packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 144-pin Fine
Pitch BGA (fp BGA).
Pin Configurations
(1,2,3)
INDEX
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
NC
NC
NC
LB
L
UB
L
CE
0L
CE
1L
SEM
L
V
DD
R/W
L
OE
L
V
SS
V
SS
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
NC
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
IDT70V27PF
PN100-1
(4)
100-PIN TQFP
TOP VIEW
(5)
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
07/29/04
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
NC
NC
NC
LB
R
UB
R
CE
0R
CE
1R
SEM
R
V
SS
R/W
R
OE
R
V
SS
V
SS
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
3603 drw 02
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
V
DD
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
SS
I/O1
L
I/O
0L
V
SS
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
V
DD
I/O
7R
I/O
8R
I/O
9R
NC
2
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Pin Configurations
(1,2,3)
(con't.)
07/29/04
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
NC
B1
NC
B2
A
8L
B3
A
5L
B4
A
1L
B5
INT
L
B6
V
SS
B7
BUSY
R
A
1R
B8
B9
A
5R
B10
NC
B11
NC
B12
NC
B13
NC
C1
NC
C2
NC
C3
A
6L
C4
A
2L
C5
NC
C6
M/S
C7
INT
R
C8
A
2R
C9
A
6R
C10
NC
C11
NC
C12
NC
C13
A
10L
D1
A
9L
D2
NC
D3
A
7L
D4
A
3L
D5
NC
D6
NC
D7
D8
NC
A
3R
D9
A
7R
D10
A
9R
D11
A
10R
D12
A
11R
D13
A
14L
E1
A
13L
E2
A
12L
E3
A
11L
E4
A
4L
A
0L
BUSY
L
A
0R
A
4R
A
8R
E10
A
12R
E11
A
13R
E12
A
14R
E13
LB
L
F1
NC
F2
F3
NC
F4
NC
UB
L
G4
NC
F10
NC
F11
NC
F12
LB
R
F13
SEM
L
CE
1L
G1
G2
CE
0L
G3
IDT70V27BF
BF144-1
(4)
UB
R
G10
CE
0R
CE
1R
SEM
R
G11
G12
G13
V
DD
H1
V
DD
H2
V
DD
H3
H4
NC
144-Pin fpBGA
Top View
(5)
NC
H10
NC
H11
V
SS
H12
V
SS
H13
NC
J1
R/W
L
J2
J3
OE
L
J4
NC
NC
J10
OE
R
J11
R/W
R
J12
V
SS
J13
V
SS
K1
I/O
15L
I/O
14L
I/0
13L
K2
K3
K4
K5
K6
K7
K8
K9
I/O
13R
I/O
14R
I/O1
5R
K10
K11
K12
V
SS
K13
I/O
12L
L1
NC
L2
NC
L3
L4
NC
I/O
6L
I/O
3L
L5
L6
I/O
0R
I/O
3R
L7
L8
I/O
6R
I/O
11R
L9
L10
NC
L11
NC
L12
I/O
12R
L13
,
I/O
11L
I/O
10L
M1
M2
NC
M3
NC
M4
I/O
5L
M5
I/O
2L
M6
V
SS
M7
V
DD
M8
I/O
5R
M9
NC
M10
NC
M11
NC
M12
I/O
10R
M13
I/O
9L
N1
NC
N2
NC
N3
V
DD
N4
I/O
4L
N5
V
SS
N6
I/O
0L
N7
I/O
2R
N8
I/O
4R
I/O
7R
N9
N10
I/O
8R
N11
NC
N12
I/O
9R
N13
NC
NC
I/O
8L
I/O
7L
NC
I/O
1L
V
DD
I/O
1R
NC
V
DD
NC
NC
NC
3603 drw 02a
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground supply.
3. Package body is approximately 12mm x 12mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
DD
V
ss
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power (3.3V)
Ground (0V)
3603 tbl 01
Names
3
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Truth Table I – Chip Enable
(1,2,3)
CE
CE
0
V
IL
L
< 0.2V
V
IH
X
H
>V
DD
-0.2V
X
NOTES:
CE
1
V
IH
>V
DD
-0.2V
X
V
IL
X
<0.2V
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Mode
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
3603 tbl 02
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE
is a reference only.
2. Port "A" and "B" references are located where
CE
is used.
3. "H" = V
IH
and "L" = V
IL
Truth Table II – Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
X
L
L
L
L
L
L
X
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
Outputs
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
3603 tbl 03
NOTES:
1. A
0L
— A
14L
≠
A
0R
— A
14R.
2. Refer to Chip Enable Truth Table.
Truth Table III – Semaphore Read/Write Control
Inputs
(1)
CE
(2)
H
X
H
X
L
L
R/W
H
H
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
Outputs
I/O
8-15
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
______
I/O
0-7
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
______
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
3603 tbl 04
↑
↑
X
X
NOTES:
1. There are eight semaphore flags written to I/O
0
and read from all the I/Os (I/O
0
-I/O
15
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
4
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
DD
3.3V
+
0.3V
3.3V
+
0.3V
3603 tbl 06
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
Industrial
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
3603 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
Recommended DC Operating
Conditions
(1)
Symbol
V
DD
V
SS
V
IH
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
Max.
3.6
0
V
DD
+0.3V
(2)
0.8
Unit
V
V
V
V
3603 tbl 07
Capacitance
Symbol
C
IN
C
OUT
(2)
(1)
V
IL
____
(T
A
= +25°C, f = 1.0mhz)TQFP ONLY
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
9
10
Unit
pF
pF
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
DD
+ 0.3V.
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. C
OUT
also reference C
I/O
.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 0.3V)
70V27S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
NOTE:
1. At
V
DD
70V27L
Min.
___
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
DD
= 3.6V, V
IN
= 0V to V
DD
CE
= V
IH
, V
OUT
= 0V to V
DD
I
OL
= 4mA
I
OH
= -4mA
Min.
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3603 tbl 09
___
___
___
___
2.4
2.4
<
2.0V, input leakages are undefined.
5
