CMOS Static RAM
1 Meg (256K x 4-Bit)
Revolutionary Pinout
Features
x
x
IDT71128
Description
The IDT71128 is a 1,048,576-bit high-speed static RAM
organized as 256K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability CMOS technology. This state-of-the-art
technology, combined with innovative circuit design techniques,
provides a cost-effective solution for high-speed memory needs.
The JEDEC centerpower/GND pinout reduces noise generation
and improves system performance.
The IDT71128 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71128 are TTL-compat-
ible and operation is from a single 5V supply. Fully static asyn-
chronous circuitry is used; no clocks or refreshes are required for
operation.
The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ.
x
x
x
x
x
256K x 4 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise.
Equal access and cycle times
— Commercial and Industrial: 12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A
0
ADDRESS
DECODER
1,048,576-BIT
MEMORY
ARRAY
.
A
17
4
4
I/O
0
- I/O
3
I/O CONTROL
CS
WE
OE
CONTROL
LOGIC
3483 drw 01
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-3483/09
IDT71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Pin Configuration
NC
A
0
A
1
A
2
A
3
CS
I/O
0
V
CC
GND
I/O
1
WE
A
4
A
5
A
6
A
7
NC
1
32
2
31
3
30
4
29
5
28
6 SO32-3 27
7
26
8
25
24
9
23
10
22
11
21
12
13
20
14
19
15
18
16
17
A
17
A
16
A
15
A
14
A
13
OE
I/O
3
GND
V
CC
I/O
2
A
12
A
11
A
10
A
9
A
8
NC
3483 drw 02
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7.0
(2)
0 to +70
-55 to +125
-55 to +125
1.25
50
Unit
V
o
o
C
C
C
o
W
mA
3483 tbl 02
SOJ
Top View
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V.
Capacitance
Truth Table
CS
L
L
L
H
V
HC
(3)
OE
L
X
H
X
X
(1,2)
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
Function
Read Data
Write Data
Output Disabled
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
3483 tbl 01
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
8
8
Unit
pF
pF
3483 tbl 03
WE
H
L
H
X
X
C
IN
C
I/O
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
-0.2V.
3. Other inputs
≥V
HC
or
≤V
LC
.
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
GND
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
3483 tbl 04
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
V
CC
+0.5
0.8
Unit
V
V
V
V
3483 tbl 05
NOTE:
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
6.42
2
IDT 71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
(V
CC
= 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
Test Conditions
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= -4mA, V
CC
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3483 tbl 06
2.4
DC Electrical Characteristics
(1)
(V
CC
= 5.0V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
71128S12
Symbol
I
CC
I
SB
Parameter
Dynamic Operating Current
CS
< V
IL
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS
> V
IH
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
Full Standby Power Supply Current (CMOS Level)
CS
> V
HC
, Outputs Open, V
CC
= Max., f = 0
(2)
V
IN
< V
LC
or V
IN
> V
HC
Com'l.
155
40
10
Ind.
155
40
10
71128S15
Com'l.
150
40
10
Ind.
150
40
10
71128S20
Com'l.
145
40
10
Ind.
145
40
10
Unit
mA
mA
mA
I
SB1
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
3483 tbl 07
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1 and 2
3483 tbl 08
AC Test Loads
5V
480Ω
DATA
OUT
30pF
255Ω
3483 drw 03
5V
480Ω
DATA
OUT
5pF*
255Ω
3483 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
6.42
3
IDT71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71128S12
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
WRITE CYCLE
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Output active from End-of-Write
Write Enable to Output in High-Z
12
10
10
0
10
0
7
0
3
0
____
____
____
____
____
____
____
____
71128S15
Min.
Max.
71128S20
Min.
Max.
Unit
Parameter
Min.
Max.
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
12
____
____
____
15
____
____
____
20
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
____
15
15
____
20
20
____
3
0
____
3
0
____
3
0
____
6
6
____
7
7
____
8
8
____
0
0
4
0
____
0
0
4
0
____
0
0
4
0
____
5
____
5
____
7
____
____
____
____
12
15
20
15
12
12
0
12
0
8
0
3
0
____
____
____
____
____
____
____
____
20
15
15
0
15
0
9
0
4
0
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3483 tbl 09
____
____
____
5
5
8
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
4
IDT 71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OLZ
(5)
(5)
(3)
t
ACS
t
CLZ
DATA
OUT
t
CHZ (5)
t
OHZ (5)
HIGH IMPEDANCE
DATA
OUT
VALID
t
PD
V
CC
SUPPLY I
CC
CURRENT I
SB
t
PU
3483 drw 05
Timing Waveform of Read Cycle No. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3483 drw 06
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
6.42
5
单片机
