HIGH-SPEED
2K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7132SA/LA
IDT7142SA/LA
FEATURES:
• High-speed access
— Military: 25/35/55/100ns (max.)
— Commercial: 25/35/55/100ns (max.)
— Commercial: 20ns only in PLCC for 7132
• Low-power operation
— IDT7132/42SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
— IDT7132/42LA
Active: 550mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• MASTER IDT7132 easily expands data bus width to 16-or-
more bits using SLAVE IDT7142
• On-chip port arbitration logic (IDT7132 only)
•
BUSY
output flag on IDT7132;
BUSY
input on IDT7142
• Battery backup operation —2V data retention
• TTL-compatible, single 5V
±10%
power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD, Class B
• Standard Military Drawing # 5962-87002
• Industrial temperature range (–40°C to +85°C) is available,
tested to miliary electrical specifications
DESCRIPTION:
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port
Static RAMs. The IDT7132 is designed to be used as a stand-
alone 8-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7142 “SLAVE” Dual-Port in 16-bit-or-
more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and l/O pins that permit independent, asyn-
chronous access for reads or writes to any location in memory.
An automatic power down feature, controlled by
CE
permits
the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 550mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each Dual-Port typically consuming 200µW
from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin
sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and
48-lead flatpacks. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
OE
L
R/
OE
R
R/
CE
L
W
L
CE
R
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
11
(1,2)
A
10L
A
0L
MEMORY
ARRAY
Address
Decoder
A
10R
A
0R
NOTES:
1. IDT7132 (MASTER):
BUSY
is open
drain output and requires pullup
resistor of 270Ω.
IDT7142 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup
resistor of 270Ω.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
11
CE
L
ARBITRATION
LOGIC
CE
R
2692 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2692/8
6.02
1
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUSY
R
BUSY
L
PIN CONFIGURATIONS
(1,2)
W
R
R/
W
L
BUSY
L
R/
CE
L
A
10L
A
10R
W
L
A
10L
BUSY
R
BUSY
L
W
L
W
R
2692 drw 02
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
7 6
A
1L
A
2L
A
3L
A
4L
A
5L
8
9
10
11
12
13
14
15
16
17
18
19
20
5 4
3 2
R/
1
52 51 50 49 48 47
46
45
44
43
42
41
40
39
38
37
36
35
34
R/
INDEX
N/C
N/C
A
10R
A
10L
V
CC
CE
R
OE
L
CE
L
A
0L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
OE
L
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
IDT7132/ 40
9
10 7142 39
11
38
12 P48-1 37
&
13 C48-2 36
14
35
15 DIP 34
16 TOP 33
17 VIEW
(3)
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
V
CC
R/
CE
R
BUSY
R
A
10R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
W
R
6 5
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
7
8
9
10
11
12
13
14
15
4 3
R/
INDEX
2
1
48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
OE
R
IDT7132/42
L48-1
&
F48-1
48-PIN LCC/ FLATPACK
TOP VIEW
(3)
16
33
17
32
18
31
19 20 21 22 23 24 25 26 27 28 29 30
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
V
CC
CE
L
CE
R
OE
R
2692 drw 03
OE
L
A
0L
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
2692 drw 04
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
IDT7132/42
J52-1
52-PIN PLCC
TOP VIEW
(3)
A
6L
A
7L
A
8L
A
9L
T
A
T
BIAS
T
STG
I
OUT
0 to +70
-55 to +125
-55 to +125
50
-55 to +125
-65 to +135
-65 to +150
50
°C
°C
°C
mA
I/O
0L
I/O
1L
I/O
2L
I/O
3L
21 22 23 24 25 26 27 28 29 30 31 32 33
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
2692 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc +
0.5V.
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min. Typ.
4.5
5.0
0
0
2.2
-0.5
(1)
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
-55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2692 tbl 02
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2692 tbl 03
—
—
NOTES:
1. V
IL
(min.) = -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
6.02
2
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1,6)
(V
CC
= 5.0V
±
10%)
7132X20
(2)
7132X25
(3)
7132X35 7132X55 7132X100
7142X25
(3)
7142X35 7142X55 7142X100
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
—
— 110 280
—
— 110 220
110 250 110 220
110 200 110 170
—
—
30
30
—
—
65
65
—
—
1.0
0.2
—
—
60
60
—
—
65
45
—
—
165
125
—
—
15
5
—
—
155
115
30
30
30
30
65
65
65
65
1.0
0.2
1.0
0.2
60
60
60
60
80
60
65
45
160
125
150
115
30
10
15
5
155
115
145
105
80
80
80
80
25
25
25
25
50
50
50
50
1.0
0.2
1.0
0.2
45
45
45
45
230
170
165
120
80
60
65
45
150
115
125
90
30
10
15
4
145
105
110
85
65
65
65
65
20
20
20
20
190
140
155
110
65
45
65
35
65
65
65
65
20
20
20
20
40
40
40
40
1.0
0.2
1.0
0.2
40
40
40
40
190
140
155
110
65
45
55
35
125
90
110
75
30
10
15
4
110
80
95
70
mA
Symbol
I
CC
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports - All
CMOS Level Inputs
Full Standby Current
(One Port - All
CMOS Level Inputs)
Test Conditions
Version
SA
LA
COM'L. SA
LA
SA
LA
COM'L. SA
LA
MIL.
MIL.
MIL.
CE
L
and
CE
R
= V
IL
,
Outputs open,
f = f
MAX
(4)
I
SB1
CE
L
and
CE
R
= V
IH
,
f = f
MAX
(4)
mA
I
SB2
SA
LA
Active Port Outputs COM'L. SA
Open, f = f
MAX
(4)
LA
CE
"
A
"
=
V
IL
and
CE
"
B
"
=
V
IH
(7)
40 125
40 90
40 110
40 75
1.0
0.2
1.0
0.2
30
10
15
4
mA
I
SB3
CE
L
and
CE
R
> V
CC
-0.2V,
V
IN
> V
CC
-0.2V or
V
IN
< 0.2V,f = 0
(5)
MIL.
SA
LA
COM'L. SA
LA
MIL.
mA
I
SB4
CE
"
A
"
<
0.2V and
CE
"
B
"
> V
CC
-0.2V
(7)
V
IN
> V
CC
-0.2V or
V
IN
< 0.2V,
Active Port Outputs
Open, f = f
MAX
(4)
SA
LA
COM'L. SA
LA
40 110
40 85
40 100
40 70
mA
NOTES:
2689 tbl 04
1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
3. Not available in DIP packages.
4. At f = f
Max
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC TEST CONDITIONS”
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = 5V, T
A
=+25°C for Typ. and is not production tested. Vcc
DC
= 100mA (Typ.)
7. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
±
10%)
7132SA
7142SA
Min.
Max.
—
—
—
—
2.4
10
10
0.4
0.5
—
7132LA
7142LA
Max.
Max.
—
—
—
—
2.4
5
5
0.4
0.5
—
Symbol
|l
Ll
|
|l
LO
|
V
OL
V
OL
V
OH
Parameter
Input Leakage
Current
(1)
Output Leakage
Current
(1)
Output Low Voltage
(l/O0-l/O
7
)
Open Drain Output
Low Voltage (
BUSY
,
INT
)
Output High Voltage
Supply Current
Test Conditions
V
CC
= 5.5V,
V
IN
= 0V to V
CCIN
= GND to V
CC
V
CC
= 5.5V,
CE
= V
IH
, V
OUT
= 0V to V
CC
C
l
OL
= 4mA
l
OL
= 16mA
l
OL
= 16mA
l
OH
= -4mA
V
IN
> V
CC
-0.2V or < 0.2V
Unit
µA
µA
V
V
V
2689 tbl 05
NOTE:
1. At Vcc
<
2.0V leakages are undefined.
6.02
3
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS
(LA Version Only)
Symbol
V
DR
I
CCDR
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Test Conditions
V
CC
= 2.0V,
CE
≥
V
CC
-0.2V
Mil.
lDT7132LA/IDT7142LA
Min.
Typ.
Max.
2.0
—
—
0
t
RC
(2)
—
100
100
—
—
—
4000
1500
—
—
Unit
V
µA
µA
ns
ns
2692 tbl 06
V
IN
≥
V
CC
-0.2V or V
IN
≤
0.2V Com’l.
t
CDR
t
R
(3)
Chip Deselect to Data
Retention Time
Operation Recovery
Time
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and is not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed but not production tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND TO 3.0V
5ns
1.5V
1.5V
Figures 1, 2, and 3
2692 tbl 07
V
CC
4.5V
t
CDR
V
DR
≥
2.0V
4.5V
t
R
CE
V
DR
V
IH
V
IH
2692 drw 05
5V
1250Ω
DATA
OUT
5V
1250Ω
DATA
30pF*
100pF for 55 and 100ns versions
OUT
775Ω
775Ω
5pF*
2692 drw 06
Figure 1. AC Output Test Load
5V
270Ω
Figure 2. Output Test Load
(for t
HZ
, t
LZ
, t
WZ
, and t
OW
)
* Including scope and jig
BUSY
or
INT
30pF*
100pF for 55 and 100ns versions
Figure 3.
BUSY
and
INT
AC Output Test Load
6.02
4
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(3)
Symbol
Read Cycle
t
RC
t
AA
t
ACE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time
(1,4)
Output High-Z Time
(1,4)
Chip Enable to Power Up Time
(4)
Chip Disable to Power Down Time
(4)
20
—
—
3
0
—
0
—
—
20
20
11
—
—
10
—
20
25
—
—
—
3
0
—
0
—
—
25
25
12
—
—
10
—
25
35
—
—
—
3
0
—
0
—
—
35
35
20
—
—
15
—
35
55
—
—
—
3
5
—
0
—
—
55
55
25
—
—
25
—
50
100
—
—
—
10
5
—
0
—
—
100
100
40
—
—
40
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
7132X20
(2)
7132X25
(5)
7132X35
7132X55
7132X100
(5)
7142X35
7142X55
7142X100
7142X25
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
NOTES:
1. Transition is measured
±500mV
from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
2689 tbl 08
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
t
OH
BUSY
OUT
t
BDDH
(2,3)
2692 drw 07
NOTES:
1. R/
W
= V
IH,
CE
= V
IL,
and is
OE
= V
IL.
Address is valid prior to the coincidental with
CE
transition Low.
2. t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read
operations,
BUSY
has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
,
t
AA
, and
t
BDD
.
6.02
5
