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IDT7164L20PE

Standard SRAM, 8KX8, 19ns, CMOS, PDSO28, 0.330 INCH, SOIC-28

器件类别:存储    存储   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
是否Rohs认证
不符合
零件包装代码
SOIC
包装说明
0.330 INCH, SOIC-28
针数
28
Reach Compliance Code
not_compliant
ECCN代码
EAR99
最长访问时间
19 ns
I/O 类型
COMMON
JESD-30 代码
R-PDSO-G28
JESD-609代码
e0
长度
18.3642 mm
内存密度
65536 bit
内存集成电路类型
STANDARD SRAM
内存宽度
8
功能数量
1
端口数量
1
端子数量
28
字数
8192 words
字数代码
8000
工作模式
ASYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
8KX8
输出特性
3-STATE
可输出
YES
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装等效代码
SOP28,.5
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
并行/串行
PARALLEL
电源
5 V
认证状态
Not Qualified
座面最大高度
3.048 mm
最大待机电流
0.00006 A
最小待机电流
2 V
最大压摆率
0.15 mA
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
宽度
8.763 mm
Base Number Matches
1
文档预览
®
CMOS STATIC RAM
64K (8K x 8-BIT)
IDT7164S
IDT7164L
Integrated Device Technology, Inc.
FEATURES:
• High-speed address/chip select access time
— Military: 20/25/30/35/45/55/70/85ns (max.)
— Commercial: 15/20/25/30/35ns (max.)
• Low power consumption
• Battery backup operation — 2V data retention voltage
(L Version only)
• Produced with advanced CMOS high-performance
technology
• Inputs and outputs directly TTL-compatible
• Three-state outputs
• Available in:
— 28-pin DIP, SOIC, SOJ, and CERPACK
— 32-pin LCC
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7164 is a 65,536 bit high-speed static RAM orga-
nized as 8K x 8. It is fabricated using IDT’s high-performance,
high-reliability CMOS technology.
Address access times as fast as 15ns are available and the
circuit offers a reduced power standby mode. When
CS
1
goes
HIGH or CS
2
goes LOW, the circuit will automatically go to,
and remain in, a low-power stand by mode. The low-power (L)
version also offers a battery backup data retention capability
at power supply levels as low as 2V.
All inputs and outputs of the IDT7164 are TTL-compatible
and operation is from a single 5V supply, simplifying system
designs. Fully static asynchronous circuitry is used, requiring
no clocks or refreshing for operation.
The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ;
28-pin 330 mil SOIC; 28-pin 600 mil DIP; 32-pin LCC; and 28-
pin CERPACK.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
ADDRESS
DECODER
A
12
65,536 BIT
MEMORY ARRAY
GND
0
7
I/O
0
I/O CONTROL
I/O
7
CS
1
CS
2
OE
WE
CONTROL
LOGIC
2967 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994
Integrated Device Technology, Inc.
MAY 1994
DSC-1002/7
6.5
1
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
14
15
I/O
1
I/O
2
GND
NC
I/O
3
I/O
4
I/O
5
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
D28-1
D28-3
E28-2
P28-1
P28-2
SO28-3
SO28-5
V
CC
WE
CS
2
A
8
A
9
A
11
OE
A
10
CS
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
7
A
12
NC
NC
V
CC
WE
CS
2
4
3
2
5
6
7
8
9
10
11
12
1
32 31 30
29
28
27
26
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
L32-1
25
24
23
22
21
13
14 15 16 17 18 19 20
A
8
A
9
A
11
NC
OE
A
10
CS
1
I/O
7
I/O
6
2967 drw 03
2967 drw 02
DIP/SOIC/SOJ/CERPACK
TOP VIEW
32-PIN LCC
TOP VIEW
PIN DESCRIPTIONS
Name
A
0
–A
12
I/O
0
–I/O
7
CS
1
TRUTH TABLE
(1,2,3)
Description
Address
Data Input/Output
Chip Select
Chip Select
Write Enable
Output Enable
Ground
Power
2967 tbl 01
WE
CS
1
CS
2
X
L
OE
I/O
High-Z
High-Z
High-Z
High-Z
High-Z
Data
IN
Function
Deselected – Standby (I
SB
)
Deselected – Standby (I
SB
)
Deselected –Standby (I
SB1
)
Deselected –Standby (I
SB1
)
Output Disabled
Write Data
2967 tbl 02
X
X
X
X
H
H
L
H
X
X
X
X
X
H
L
X
CS
2
WE
OE
V
HC
V
HC
or
V
LC
X
L
L
L
V
LC
H
H
H
GND
VCC
Data
OUT
Read Data
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Com’l.
–0.5 to +7.0
Mil.
–0.5 to +7.0
Unit
V
V
TERM
(2)
Terminal Voltage
with Respect
to GND
T
A
T
BIAS
T
STG
P
T
I
OUT
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output
Current
NOTES:
1. CS
2
will power-down
CS
1
, but
CS
1
will not power-down CS
2
.
2. H = V
IH
, L = V
IL
, X = don't care.
3. V
LC
= 0.2V, V
HC
= V
CC
- 0.2V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
VCC
5V
±
10%
5V
±
10%
2967 tbl 05
0 to +70
–55 to +125
–55 to +125
1.0
50
–55 to +125
–65 to +135
–65 to +150
1.0
50
°C
°C
°C
W
mA
Military
Commercial
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
Max.
5.5
0
0.8
Unit
V
V
V
NOTES:
2967 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed VCC + 0.5V.
— V
CC
+ 0.5 V
NOTE:
2967 tbl 06
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
6.5
2
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
NOTE:
2967 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5.0V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
7164S15
7164L15
Symbol
I
CC1
Parameter
Operating Power Supply
Current,
CS
1
= V
IL
, CS
2
= V
IH
,
Outputs Open, V
CC
= Max., f = 0
(3)
Dynamic Operating Current
CS
1
= V
IL
, CS
2
= V
IH
,
Outputs Open, V
CC
= Max., f = f
MAX
(3)
Standby Power Supply Current
(TTL Level),
CS
1
V
IH
or CS
2
V
IL
V
CC
= Max., Outputs Open, f = f
MAX
(3)
Full Standby Power Supply Current
(CMOS Level), f = 0
(3)
, V
CC
= Max.
1.
CS
1
V
HC
and CS
2
V
HC
, or
2. CS
2
V
LC
Power Com’l. Mil.
S
L
S
L
S
L
S
L
110
100
180
150
20
3
15
0.2
7164S20
7164L20
Com’l.
100
90
170
150
20
3
15
0.2
Mil.
110
100
180
160
20
5
20
1
7164S25
7164L25
Com’l.
90
80
170
150
20
3
15
0.2
Mil.
110
100
180
160
20
5
20
1
7164S30
7164L30
Com’l.
90
80
160
140
20
3
15
0.2
Mil.
100
90
170
150
20
5
20
1
mA
mA
mA
Unit
mA
I
CC2
I
SB
I
SB1
DC ELECTRICAL CHARACTERISTICS
(1)
(Continued)
(V
CC
= 5.0V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
7164S35
7164L35
Symbol
I
CC1
Parameter
Operating Power Supply
Current,
CS
1
= V
IL
, CS
2
= V
IH
,
Outputs Open, V
CC
= Max., f = 0
(3)
Dynamic Operating Current
CS
1
= V
IL
, CS
2
= V
IH
,
Outputs Open, V
CC
= Max., f = f
MAX(3)
Standby Power Supply Current
(TTL Level),
CS
1
V
IH
, or CS
2
V
IL
V
CC
= Max., Outputs Open, f = f
MAX(3)
Full Standby Power Supply Current
(CMOS Level), f = 0
(3)
, V
CC
= Max.
1.
CS
1
V
HC
and CS
2
V
HC
, or
2. CS
2
V
LC
Power Com’l. Mil.
S
L
S
L
S
L
S
L
90
80
150
130
20
3
15
0.2
100
90
160
140
20
5
20
1
7164S45
7164L45
Com’l.
Mil.
100
90
160
130
20
5
20
1
7164S55
7164L55
Com’l.
Mil.
100
90
160
125
20
5
20
1
7164S70/85
(2)
7164L70/85
(2)
Com’l.
Mil.
100
90
160
120
20
5
20
1
2967 tbl 07
Unit
mA
I
CC2
mA
I
SB
mA
I
SB1
mA
NOTES:
1. All values are maximum guaranteed values.
2. Also available: 100, 120, 150 and 200ns military devices.
3. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
6.5
3
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%)
IDT7164S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Condition
V
CC
= Max.,
V
IN
= GND to V
CC
V
CC
= Max.,
CS
1
= V
IH,
V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OL
= 10mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= –4mA, V
CC
= Min.
2.4
MIL.
COM’L.
MIL.
COM’L.
Min.
Max.
10
5
10
5
0.4
0.5
IDT7164L
Min.
2.4
Max.
5
2
5
2
0.4
0.5
V
Unit
µA
µA
V
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) (V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR(3)
t
R(3)
|I
LI
|
(3)
Max.
V
CC
@
2.0V
200
60
2
3.0V
300
90
2
Unit
V
µA
ns
ns
µA
2967 tbl 10
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Input Leakage Current
Test Condition
MIL.
COM’L.
1.
CS
1
V
HC
CS
2
V
HC
, or
2. CS
2
V
LC
Min.
2.0
0
t
RC(2)
2.0v
10
10
3.0V
15
15
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2967 tbl 08
5V
480Ω
DATA
OUT
255Ω
30pF*
5V
480
DATA
OUT
255
5pF*
2967 drw 06
2967 drw 07
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ1,
t
CLZ2
, t
OLZ
, t
CHZ1,
t
CHZ2
, t
OHZ
, t
OW
, and t
WHZ
)
*Includes scope and jig capacitances
6.5
4
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
7164S15
(1)
7164L15
(1)
Symbol
Read Cycle
t
RC
t
AA
t
ACS1(3)
t
ACS2(3)
Read Cycle Time
Address Access Time
Chip Select-1 Access Tim
Chip Select-2 Access Time
15
5
0
5
0
15
15
20
7
8
7
15
20
5
0
5
0
19
20
25
8
9
8
20
25
5
0
5
0
25
25
30
12
13
10
25
30
5
0
5
0
29
30
35
15
13
12
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
Max.
7164S20
7164L20
Min.
Max.
7164S25
7164L25
Min.
Max.
7164S30
7164L30
Min.
Max.
Unit
t
CLZ1,2(4)
Chip Select-1, 2 to Output in Low-Z
t
OE
t
OLZ(4)
t
OHZ(4)
t
OH
t
PU(4)
t
PD(4)
Output Enable to Output Valid
Output Enable to Output in Low-Z
t
CHZ1,2(4)
Chip Select-1, 2 to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
Write Cycle
t
WC
t
CW1, 2
t
AW
t
AS
t
WP
t
WR1
t
WR2
t
WHZ(4)
t
DW
t
DH1
t
DH2
t
OW(4)
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time (
CS
1
,
WE
)
Write Recovery Time (CS
2
)
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time (
CS
1
,
WE
)
Data Hold from Write Time (CS
2
)
Output Active from End-of-Write
15
14
14
0
14
0
5
8
0
5
4
6
20
15
15
0
15
0
5
10
0
5
4
8
25
18
18
0
21
0
5
13
0
5
4
10
30
22
22
0
23
0
5
13
0
5
4
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2967 tbl 11
NOTES:
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only. Also available: 100, 120, 150 and 200ns military devices.
3. Both chip selects must be active for the device to be selected.
4. This parameter is guaranteed by device characterization, but is not production tested.
6.5
5
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