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IDT7164L70TDB

Standard SRAM, 8KX8, 70ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

器件类别:存储    存储   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
IDT (Integrated Device Technology)
零件包装代码
DIP
包装说明
DIP, DIP28,.3
针数
28
Reach Compliance Code
not_compliant
ECCN代码
3A001.A.2.C
Date Of Intro
1988-01-01
最长访问时间
70 ns
I/O 类型
COMMON
JESD-30 代码
R-CDIP-T28
JESD-609代码
e0
长度
37.1475 mm
内存密度
65536 bit
内存集成电路类型
STANDARD SRAM
内存宽度
8
功能数量
1
端口数量
1
端子数量
28
字数
8192 words
字数代码
8000
工作模式
ASYNCHRONOUS
最高工作温度
125 °C
最低工作温度
-55 °C
组织
8KX8
输出特性
3-STATE
可输出
YES
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DIP
封装等效代码
DIP28,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
并行/串行
PARALLEL
峰值回流温度(摄氏度)
225
电源
5 V
认证状态
Not Qualified
筛选级别
MIL-STD-883 Class B
座面最大高度
5.08 mm
最大待机电流
0.0002 A
最小待机电流
2 V
最大压摆率
0.12 mA
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
20
宽度
7.62 mm
文档预览
CMOS Static RAM
64K (8K x 8-Bit)
Features
Description
IDT7164S
IDT7164L
High-speed address/chip select access time
– Military: 20/25/35/45/55/70/85/100ns (max.)
– Industrial: 20/25ns (max.)
– Commercial: 20/25ns (max.)
Low power consumption
Battery backup operation – 2V data retention voltage
(L Version only)
Produced with advanced CMOS high-performance
technology
Inputs and outputs directly TTL-compatible
Three-state outputs
Available in 28-pin DIP, CERDIP and SOJ
Military product compliant to MIL-STD-883, Class B
The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K
x 8. It is fabricated using high-performance, high-reliability CMOS tech-
nology.
Address access times as fast as 20ns are available and the circuit offers
a reduced power standby mode. When
CS
1
goes HIGH or CS
2
goes
LOW, the circuit will automatically go to, and remain in, a low-power stand-
by mode. The low-power (L) version also offers a battery backup data
retention capability at power supply levels as low as 2V.
All inputs and outputs of the IDT7164 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ and a 28-
pin 600 mil CERDIP.
Military grade product is manufactured in compliance with MIL-STD-
883, Class B, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
Functional Block Diagram
A
0
V
CC
ADDRESS
DECODER
65,536 BIT
MEMORY ARRAY
GND
A
12
0
7
I/O
0
I/O CONTROL
I/O
7
CS
1
CS
2
OE
WE
CONTROL
LOGIC
2967 drw 01
OCTOBER 2013
1
©2013 Integrated Device Technology, Inc.
DSC-2967/16
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Pin Configurations
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Absolute Maximum Ratings
(1)
Symbol
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com'l.
-0.5 to +7.0
Mil.
-0.5 to +7.0
Unit
V
D28-1
D28-3
P28-2
SO28-5
V
CC
WE
CS
2
A
8
A
9
A
11
OE
A
10
CS
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
2967 drw 02a
V
TERM
(2)
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
-55 to +125
-55 to +125
1.0
50
-55 to +125
-65 to +135
-65 to +150
1.0
50
o
C
C
C
o
o
W
mA
2967 tbl 02
DIP/SOJ
Top View
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
Pin Descriptions
Name
A
0
- A
12
I/O
0
- I/O
7
CS
1
CS
2
WE
OE
GND
V
CC
Description
Address
Data Input/Output
Chip Select
Chip Select
Write Enable
Output Enable
Ground
Power
2967 tbl 01
Truth Table
(1,2,3)
WE
X
X
X
X
H
H
L
CS
1
H
X
V
HC
X
L
L
L
CS
2
X
L
V
HC
or
V
LC
V
LC
H
H
H
OE
X
X
X
X
H
L
X
I/O
High-Z
High-Z
High-Z
High-Z
High-Z
DATA
OUT
DATA
IN
Function
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
Deselected - Standby (I
SB1
)
Output Disabled
Read Data
Write Data
2967 tbl 03
NOTES:
1. CS
2
will power-down
CS
1
, but
CS
1
will not power-down CS
2
.
2. H = V
IH
, L = V
IL
, X = don't care.
3. V
LC
= 0.2V, V
HC
= V
CC
- 0.2V
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input HIGH Voltage
Input LOW Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
V
CC
+ 0.5
0.8
Unit
V
V
V
V
2967 tbl 05
Recommended Operating
Temperature and Supply Voltage
Grade
Military
Industrial
Commercial
Temperature
-55
O
C to +125
O
C
-40
O
C to +85
O
C
0
O
C to +70
O
C
GND
0V
0V
0V
Vcc
5V ± 10%
5V ± 10%
5V ± 10%
2967 tbl 04
NOTE:
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
2
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
2967 tbl 06
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
DC Electrical Characteristics
(1)
(V
CC
= 5.0V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
7164S20
7164L20
7164S25
7164L25
Mi l .
110
100
180
160
20
5
20
1
Com'l.
90
90
170
150
20
3
15
0.2
Ind.
110
100
170
150
20
3
15
0.2
Mi l .
110
100
180
160
20
5
20
1
2967 tb l 07
Symbol
I
CC1
Parameter
Op e rating Po we r Sup p ly Curre nt
CS
1
= V
IL
, CS
2
= V
IH
, Outp uts Op e n
V
CC
= Max., f
=
0
(2)
Dynamic Op e rating Curre nt
CS
1
= V
IL
, CS
2
= V
IH
, Outp uts Op e n
V
CC
= Max., f = f
MAX
(2)
Stand b y Po we r Sup p ly Curre nt
(TTL Le ve l),
CS
1
> V
IH
, CS
2
< V
IL
,
Outp uts Op e n, V
CC
= Max., f = f
MAX
(2)
Full Stand b y Po we r Sup p ly Curre nt
(CMOS Le ve l), f = 0
(2)
, V
CC
= Max.
1.
CS
1
> V
HC
and CS
2
> V
HC
, o r
2. CS
2
< V
LC
Power
S
L
S
L
S
L
S
L
Com'l.
100
90
170
150
20
3
15
0.2
Ind.
110
100
170
150
20
3
15
0.2
Unit
mA
I
CC2
mA
I
SB
mA
I
SB1
mA
7164S35
7164L35
Symbol
I
CC1
Parameter
Op e rating Po we r Sup p ly Curre nt
CS
1
= V
IL
, CS
2
= V
IH
, Outp uts Op e n
V
CC
= Max., f
=
0
(2)
Dynamic Op e rating Curre nt
CS
1
= V
IL
, CS
2
= V
IH
, Outp uts Op e n
V
CC
= Max., f = f
MAX
(2)
Stand b y Po we r Sup p ly Curre nt
(TTL Le ve l),
CS
1
> V
IH
, CS
2
< V
IL
,
Outp uts Op e n, V
CC
= Max., f = f
MAX
(2)
Full Stand b y Po we r Sup p ly Curre nt
(CMOS Le ve l), f = 0
(2)
, V
CC
= Max.
1.
CS
1
> V
HC
and CS
2
> V
HC
, o r
2. CS
2
< V
LC
Power
S
L
S
L
S
L
S
L
Mi l .
100
90
160
140
20
5
20
1
7164S45
7164L45
Mi l .
100
90
160
130
20
5
20
1
7164S55
7164L55
Mi l .
100
90
160
125
20
5
20
1
7164S70
7164L70
Mi l .
100
90
160
120
20
5
20
1
7164S85/100
7164L85/100
Mi l .
100
90
160
120
20
5
20
1
2967 tb l 08
Unit
mA
I
CC2
mA
I
SB
mA
I
SB1
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
6.42
3
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DC Electrical Characteristics
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
(V
CC
= 5.0V ± 10%)
IDT7164S
IDT7164L
Min.
____
____
____
____
____
____
Test Conditions
V
CC
= Max.,
V
IN =
GND to V
CC
V
CC
= Max.,
CS
1
= V
IH
,
V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OL
= 10mA, V
CC
= Min.
MIL.
COM'L. & IND
MIL.
COM'L. & IND
Min.
____
____
____
____
____
____
Max.
10
5
10
5
0.4
0.5
____
Max.
5
2
5
2
0.4
0.5
____
Unit
µA
µA
V
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
2.4
2.4
V
2967 tbl 09
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR
(3)
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Input Leakage Current
Test Condition
____
Max.
V
CC
@
3.0V
____
Min.
2.0
____
____
2.0V
____
2.0V
____
3.0V
____
Unit
V
µA
ns
ns
µA
2967 tbl 10
MIL.
COM'L. & IND
1.
CS
1
> V
HC
CS
2
> V
HC
, or
2. CS
2
< V
LC
10
10
____
15
15
____
200
60
____
300
90
____
0
t
RC
(2)
____
____
____
____
____
I
I
LI
I
(3)
____
____
2
2
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2967 tbl 11
5V
480Ω
DATA
OUT
255Ω
30pF*
,
5V
480Ω
DATA
OUT
255Ω
5pF*
,
2967 drw 04
2967 drw 03
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ1,
t
CLZ2
, t
OLZ
, t
CHZ1,
t
CHZ2
, t
OHZ
, t
OW
, and t
WHZ
)
*Includes scope and jig capacitances
4
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5.0V ± 10%, All Temperature Ranges)
7164S20
7164L20
Symbol
Parameter
M i n.
Max.
7164S25
7164L25
Min.
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS1
(1)
t
ACS2
(1)
t
CLZ1,2
(2)
t
OE
t
OLZ
(2)
t
CHZ1,2
(2)
t
OHZ
(2)
t
OH
t
PU
(2)
t
PD
(2)
Re ad Cycle Time
Ad d re ss Acce ss Time
Chip Se le ct-1 Acce ss Time
Chip Se le ct-2 Acce ss Time
Chip Se le ct-1, 2 to Outp ut in Lo w-Z
Outp ut Enab le to Outp ut Valid
Outp ut Enab le to Outp ut in Lo w-Z
Chip Se le ct-1,2 to Outp ut in Hig h-Z
Outp ut Disab le to Outp ut in Hig h-Z
Outp ut Ho ld fro m Ad d re ss Chang e
Chip Se le ct to Po we r Up Time
Chip De se le ct to Po we r Do wn Time
20
____
____
25
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19
20
25
____
25
25
30
____
____
____
____
____
5
____
5
____
8
____
12
____
0
____
0
____
9
8
____
13
10
____
____
____
5
0
____
5
0
____
____
____
20
25
Write Cycle
t
WC
t
CW1,2
t
AW
t
AS
t
WP
t
WR1
t
WR2
t
WHZ
(2)
t
DW
t
DH1
t
DH2
t
OW
(2)
Write Cycle Time
Chip Se le ct to End -o f-Write
Ad d re ss Valid to End -o f-Write
Ad d re ss Se t-up Time
Write Pulse Wid th
Write Re co ve ry Time (
CS
1
,
WE
)
Write Re co ve ry Time (CS
2
)
Write Enab le to Outp ut in Hig h-Z
Data to Write Time Ove rlap
Data Ho ld fro m Write Time (
CS
1
,
WE
)
Data Ho ld fro m Write Time (CS
2
)
Outp ut Active fro m End -o f-Write
20
15
15
0
15
0
5
____
____
25
18
18
0
21
0
5
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2967 tb l 12
____
____
____
____
____
____
____
____
____
____
____
____
8
____
10
____
10
0
5
4
13
0
5
4
____
____
____
____
____
____
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
6.42
5
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