128K x 8 3.3V SYNCHRONOUS SRAM
WITH ZBT™ AND FLOW-THROUGH
OUTPUT
Integrated Device Technology, Inc.
ADVANCE
INFORMATION
IDT71V509
FEATURES:
•
•
•
•
•
•
•
128K x 8 memory configuration
High speed - 66 MHz (9 ns Clock-to-Data Access)
Flow-Through Output
No dead cycles between Write and Read Cycles
Low power deselect mode
Single 3.3V power supply (±5%)
Packaged in 44-lead SOJ
DESCRIPTION:
The IDT71V509 is a 3.3V high-speed 1,024,576-bit syn-
chronous SRAM organized as 128K x 8. It is designed to
eliminate dead cycles when turning the bus around between
reads and writes, or writes and reads. Thus, it has been given
the name ZBT™ , or Zero Bus Turnaround™ .
Addresses and control signals are applied to the SRAM
during one clock cycle, and one clock cycle later its associated
data cycle occurs, be it read or write.
The IDT71V509 contains data, address, and control signal
registers. Output Enable is the only asynchronous signal, and
can be used to disable the output at any time.
A Clock Enable (
CEN
) pin allows operation of the IDT71V509
to be suspended as long as necessary. All synchronous
inputs are ignored when
CEN
is high. A Chip Select (
CS
) pin
allows the user to deselect the device when desired. If
CS
is
high, no new memory operation is initiated, but any pending
data transfers (reads and writes) will still be completed.
The IDT71V509 utilizes IDT's high-performance 3.3V CMOS
process, and is packaged in a JEDEC Standard 400-mil 44-
lead small outline J-lead plastic package (SOJ) for high board
density.
FUNCTIONAL BLOCK DIAGRAM
Address
D
Q
Address
SRAM
Control
(
WE
,
CS
,
CEN
)
D
Input Register
Q
Control
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
Clock
OE
Gate
Data
3618 drw 01
The IDT logo is a registered trademark and CacheRAM, Zero Bus Turnaround and ZBTare trademarks of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
AUGUST 1996
11.3
DSC-3618/1
1
IDT71V509
128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
A0
A1
A2
VSS
I/O7
I/O6
VDD
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
(4)
A16
A15
A14
A13
A12
A11
WE
OE
VDD
VSS
VSS
I/O3
I/O2
VDD
I/O1
I/O0
VSS
(2)
NC
A3
A4
SO44-1
VDD
CLK
VSS
VDD
(1)
NC
(5)
CS
CEN
A10
A9
A8
A7
A6
A5
(3)
NC
Notes:
1. Pin 32: Future control input
2. Pin 20: Future I/O8
3. Pin 23: Future A17
4. Pin 44: Future A18
5. Pin 36 does not need to be connected directly to VDD, as long as it is
≥
VIH.
TOP VIEW
PIN DEFINITIONS
(1)
Symbol
A
0
-A
16
CLK
Pin Function
Address Inputs
Clock
Clock Enable
I/O
I
I
I
Active
N/A
N/A
LOW
3618 drw 02
Description
Synchronous Address inputs. The address is registered on every rising edge
of CLK if
CEN
and
CS
are both low.
Synchronous clock enable input. When
CEN
is sampled high, the other
synchronous inputs are ignored, and outputs remain unchanged. When
CEN
is sampled low, the IDT71V509 operates normally.
CEN
CS
WE
OE
I/O
0
-I/O
7
V
DD
V
SS
The clock input. Except for
OE
, all input and output timing references for the
device are with respect to the rising edge of CLK.
Chip Select
I
LOW
Write Enable
I
LOW
Synchronous write enable. If
WE
is sampled low, a write is initiated at the
address that is registered at that time. If
WE
is sampled high, a read is initiated
at the address that is registered at that time.
WE
is ignored when either
CEN
or
CS
is sampled high.
Asynchronous output enable. When
OE
is high, the I/O bus goes high
impedance.
OE
must be low to read data from the IDT71V509.
Synchronous chip select input. When
CS
is sampled low, the device operates
normally. When
CS
is sampled high, no read or write operation is initiated,
and the I/O bus is tri-stated the next cycle.
CS
is ignored if
CEN
is high at
the same rising edge of CLK.
Output Enable
Data Input/Output
Power Supply
Ground
I
I/O
N/A
N/A
LOW
N/A
N/A
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
3.3V power supply pins.
Ground pins.
11.3
2
IDT71V509
128K X 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL TIMING DIAGRAM
CYCLE
CLOCK
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
ADDRESS
(A0 - A16)
A29
A30
A31
A32
A33
A34
A35
A36
A37
CONTROL
(
CS
,
CEN
,
WE
)
DATA
(I/O0 - I/O7)
C29
C30
C31
C32
C33
C34
C35
C36
C37
D28
D29
D30
D31
D32
D33
D34
D35
D36
3618 drw 03
TYPICAL OPERATION -
CS
AND
CEN
ARE LOW
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
n+20
n+21
Address
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
WE
H
L
H
L
H
L
H
L
H
L
H
H
L
L
H
H
H
L
L
L
H
H
CS
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OE
?
L
X
L
X
L
X
L
X
L
X
L
L
X
X
L
L
L
X
X
X
L
I/O
D-1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
Comments
?
Data Out
Data In
Data Out
Data In
Data Out
Data In
Data Out
Data In
Data Out
Data In
Data Out
Data Out
Data In
Data In
Data Out
Data Out
Data Out
Data In
Data In
Data In
Data Out
11.3
3
IDT71V509
128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT
COMMERCIAL TEMPERATURE RANGE
READ OPERATION
Cycle
n
n+1
Address
A0
X
WE
H
X
CS
L
X
CEN
L
X
OE
X
L
I/O
X
D0
Comments
Address and Control meet setup
Contents of Address A0 Read Out
3618 tbl 02
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
WRITE OPERATION
Cycle
n
n+1
Address
A0
X
WE
L
X
CS
L
X
CEN
L
L
OE
X
X
I/O
X
D0
Comments
Address and Control meet setup
New Data Drives SRAM Inputs
3618 tbl 03
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
READ OPERATION WITH CLOCK ENABLE USED
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Address
A0
X
A2
X
X
A5
A6
A7
WE
H
X
H
X
X
H
H
?
CS
L
X
L
X
X
L
L
L
CEN
L
H
L
H
H
L
L
L
OE
X
L
L
L
L
L
L
L
I/O
X
D0
D0
D2
D2
D2
D5
D6
Comments
Address and Control meet setup
Contents of Address A0 Read Out
Contents of Address A0 Read Out
Contents of Address A2 Read Out
Contents of Address A2 Read Out
Contents of Address A2 Read Out
Contents of Address A5 Read Out
Contents of Address A6 Read Out
3618 tbl 04
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
WRITE OPERATION WITH CLOCK ENABLE USED
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Address
A0
X
A2
X
X
A5
A6
A7
WE
L
X
L
X
X
L
L
?
CS
L
X
L
X
X
L
L
L
CEN
L
H
L
H
H
L
L
L
OE
X
X
X
X
X
X
X
X
I/O
X
X
D0
X
X
D2
D5
D6
Comments
Address and Control meet setup
Clock Ignored at n+1 to n+2 Low-to-High
New Data Drives SRAM Inputs
Clock Ignored at n+3 to n+4 Low-to-High
Clock Ignored at n+4 to n+5 Low-to-High
New Data Drives SRAM Inputs
New Data Drives SRAM Inputs
New Data Drives SRAM Inputs
3618 tbl 05
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
11.3
4
IDT71V509
128K X 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT
COMMERCIAL TEMPERATURE RANGE
READ OPERATION WITH CHIP SELECT USED
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Address
X
X
A2
X
A4
X
X
A7
X
X
WE
X
X
H
X
H
X
X
H
X
X
CS
H
H
L
H
L
H
H
L
H
H
CEN
L
L
L
L
L
L
L
L
L
L
OE
X
X
X
L
X
L
X
X
L
X
I/O
?
Z
Z
D2
Z
D4
Z
Z
D7
Z
Comments
Deselected
Deselected
Address and Control meet setup
Deselected, Contents of Address A2 Read Out
Address and Control meet setup
Deselected, Contents of Address A4 Read Out
Deselected
Address and Control meet setup
Deselected, Contents of Address A7 Read Out
Deselected
3618 tbl 06
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
WRITE OPERATION WITH CHIP SELECT USED
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Address
X
X
A2
X
A4
X
X
A7
X
X
WE
X
X
L
X
L
X
X
L
X
X
CS
H
H
L
H
L
H
H
L
X
X
CEN
L
L
L
L
L
L
L
L
L
L
OE
X
X
X
X
X
X
X
X
X
X
I/O
?
Z
Z
D2
Z
D4
Z
Z
D7
Z
Comments
Deselected
Deselected
Address and Control meet setup
Deselected, New Data Drives SRAM Inputs
Address and Control meet setup
Deselected, New Data Drives SRAM Inputs
Deselected
Address and Control meet setup
Deselected, New Data Drives SRAM Inputs
Deselected
3618 tbl 07
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
11.3
5
