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128K x 36, 3.3V Synchronous

IDT71V546S/XS

SRAM with ZBT™ Feature,

™

Burst Counter and Pipelined Outputs

Features

128K x 36 memory configuration, pipelined outputs

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized registered outputs eliminate the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

Packaged in a JEDEC standard 100-pin TQFP package

clock cycle, and two cycles later its associated data cycle occurs, be it

read or write.

The IDT71V546 contains data I/O, address and control signal regis-

ters. Output enable is the only asynchronous signal and can be used to

disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V546 to be

suspended as long as necessary. All synchronous inputs are ignored

when

CEN

is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the user

to deselect the device when desired. If any one of these three is not active

when ADV/LD is low, no new memory operation can be initiated and any

burst that was in progress is stopped. However, any pending data

transfers (reads or writes) will be completed. The data bus will tri-state two

cycles after the chip is deselected or a write initiated.

The IDT71V546 has an on-chip burst counter. In the burst mode, the

IDT71V546 can provide four cycles of data for a single address presented

to the SRAM. The order of the burst sequence is defined by the

LBO

input

pin. The

LBO

pin selects between linear and interleaved burst sequence.

The ADV/LD signal is used to load a new external address (ADV/LD =

LOW) or increment the internal burst counter (ADV/LD = HIGH).

The IDT71V546 SRAM utilizes IDT's high-performance, high-volume

3.3V CMOS process, and is packaged in a JEDEC standard 14mm x

20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.

◆

Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM organized as 128K x 36 bits. It is designed to

eliminate dead bus cycles when turning the bus around between reads

and writes, or writes and reads. Thus it has been given the name ZBT

or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one

Pin Description Summary

- A

, CE

R/W

CEN

CLK

ADV/LD

LBO

I/O

- I/O

, I/O

- I/O

Address Inputs

Three Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance Burst Address / Load New Address

Linear / Interleaved Burst Order

Data Input/Output

3.3V Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Synchronous

Static

3821 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

OCTOBER 2008

DSC-3821/05

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT™ Feature, Burst Counter and Pipelined Outputs

™

Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

Symbol

- A

Pin Function

Address Inputs

I/O

Active

N/A

Description

Synchronous Address inputs. The address register is triggered by a

combination of the rising edge of CLK and ADV/LD Low,

CEN

Low and true

chip enables.

ADV/LD is a synchronous input that is used to load the internal registers with

new address and control when it is sampled low at the rising edge of clock with

the chip selected. When ADV/LD is low with the chip deselected, any burst in

progress is terminated. When ADV/LD is sampled high then the internal burst

counter is advanced for any burst that was in progress. The external addresses

are ignored when ADV/LD is sampled high.

R/W signal is a synchronous input that identified whether the current load cycle

initiated is a Read or Write access to the memory array. The data bus activity for

the current cycle takes place two clock cycles later.

Synchrono us Clock Enable Input. When

CEN

is sampled high, all other

synchronous inputs, including clock are ignored and outputs remain unchanged.

The effect of

CEN

samp led high on the device outputs is as if the low to high

clock transition did not occur. For normal operation,

CEN

must be sampled low

at rising edge of clock.

Synchronous byte write enables. Enable 9-bit byte has its own active low byte

write enable. On load write cycles (When R/W and ADV/LD are sampled low)

the appropriate byte write signal (BW

) must be valid. The byte write

signal must also be valid on each cycle of a burs t write. Byte Write signals are

ignored when R/W is sampled high. The appropriate byte(s) of data are written

into the device two cycles later.

can all be tied low if always doing

write to the entire 36-bit word.

Synchronous active low chip enable.

and

are used with CE

enable the IDT71V546. (CE

sampled high or CE

sampled low) and

ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT™

has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after

deselect is initiated.

Synchronout active high chip enable. CE

is used with

and

to enable

the chip. CE

has inverted polarity but otherwise identical to

and

This is the clock input to the IDT71V546. Except for

OE,

all timing references for

the device are made with respect to the rising edge of CLK.

Synchronous data input/output (I/O) pins. Both the data input path and data

output path are registered and triggered by the rising edge of CLK.

Burst order selection input. When

LBO

is high the Interleaved burst sequence is

selected. When

LBO

is low the Linear burst sequence is selected.

LBO

is a

static DC input.

Asynchronous output enable.

must be low to read data from the 71V546.

When

is high the I/O pins are in a high-impedance state.

does not need

to be actively controlled for read and write cycles. In normal operation,

can

be tied low.

3.3V power supply input.

Ground pin.

3821 tbl 02

ADV/LD

Address/Load

N/A

R/W

Read/Write

N/A

CEN

Clock Enable

LOW

Individual Byte

Write Enables

LOW

Chip Enables

LOW

CE2

CLK

I/O

- I/O

I/O

P1 -

I/O

LBO

Chip Enable

Clock

Data Input/Output

Linear Burst

Order

Output Enable

I/O

HIGH

N/A

LOW

Power Supply

Ground

N/A

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT™ Feature, Burst Counter and Pipelined Outputs

™

Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

Address A [0:16]

, CE

R/W

CEN

ADV/LD

BWx

Clk

Input Register

128K x 36 BIT

MEMORY ARRAY

Address

Control

Control Logic

Mux

Sel

Clk

Clock

Output Register

Gate

3821 drw 01

Data I/O [0:31], I/O P[1:4]

6.42

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT™ Feature, Burst Counter and Pipelined Outputs

™

Commercial and Industrial Temperature Ranges

Pin Configuration — 128K X 36

CLK

R/W

CEN

ADV/LD

(2)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/O

(1)

I/O

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PK100-1

I/O

LBO

100 TQFP

iew

Top View

NOTES:

1. Pin 14 does not have to be connected directly to V

as long as the input voltage is > V

2. Pins 83 and 84 are reserved for future A

(8M) and A

(16M) respectively.

3821 drw 02

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT™ Feature, Burst Counter and Pipelined Outputs

™

Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

(1)

Symbol

TERM

(2)

Rating

Terminal Voltage

with Respect to GND

Terminal Voltage

with Respect to GND

Commercial

Operating Ambient

Temperature

Commercial &

Industrial Values

-0.5 to +4.6

-0.5 to V

+0.5

Unit

Recommended DC Operating

Conditions

Symbol

(3)

Parameter

Supply Voltage

Ground

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

Min.

3.135

2.0

-0.5

(1)

Typ.

3.3

____

Max.

3.465

4.6

+0.3

(2)

0.8

Unit

TERM

(3)

0 to +70

(4)

Industrial

Operating Ambient

Temperature

BIAS

STG

OUT

Temperature Under Bias

Storage Temperature

Power Dissipation

DC Output Current

-40 to +85

-55 to +125

2.0

3821 tbl 04

NOTES:

1. V

(min.) = –1.0V for pulse width less than t

CYC/2

, once per cycle.

2. V

(max.) = +6.0V for pulse width less than t

CYC/2

, once per cycle.

3. V

needs to be ramped up smoothly to the operating level. If there are any

glitches on V

that cause the voltage level to drop below 2.0 volts then the

device needs to be reset by holding V

to 0.0 volts for a minimum of 100 ms.

3821 tbl 05

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

2. V

and Input terminals only.

3. I/O terminals.

4. During production testing, the case temperature equals the ambient temperature.

Recommended Operating

Temperature and Supply Voltage

Grade

Commercial

Industrial

Ambient

Temperature

(1)

C to +70

-40

C to +85

3.3V±5%

3821 tbl 03

NOTES:

1. During production testing, the case temperature equals the ambient temperature.

100 TQFP Capacitance

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

= +25°C, f = 1.0MHz, TQFP package)

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

3821 tbl 06

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

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