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CMOS ASYNCHRONOUS FIFO

32,768 x 9

Integrated Device Technology, Inc.

IDT7207

FEATURES:

• 32768 x 9 storage capacity

• High-speed: 15ns access time

• Low power consumption

— Active: 660mW (max.)

— Power-down: 44mW (max.)

• Asynchronous and simultaneous read and write

• Fully expandable in both word depth and width

• Pin and functionally compatible with IDT720x family

• Status Flags: Empty, Half-Full, Full

• Retransmit capability

• High-performance CMOS technology

• Military product compliant to MIL-STD-883, Class B

• Industrial temperature range (-40

C to +85

C) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT7207 is a monolithic dual-port memory buffer with

internal pointers that load and empty data on a first-in/first-out

basis. The device uses Full and Empty flags to prevent data

overflow and underflow and expansion logic to allow for

unlimited expansion capability in both word size and depth.

Data is toggled in and out of the device through the use of

the Write ( ) and Read ( ) pins.

The devices 9-bit width provides a bit for a control or parity

at the user’s option. It also features a Retransmit ( ) capa-

bility that allows the read pointer to be reset to its initial position

when

is pulsed LOW. A Half-Full Flag is available in the

single device and width expansion modes.

The IDT7207 is fabricated using IDT’s high-speed CMOS

technology. It is designed for applications requiring asynchro-

nous and simultaneous read/writes in multiprocessing, rate

buffering, and other applications.

Military grade product is manufactured in compliance with

the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

WRITE

CONTROL

DATA INPUTS

–D

)

WRITE

POINTER

RAM ARRAY

32,768 x 9

READ

POINTER

THREE-

STATE

BUFFERS

DATA OUTPUTS

–Q

)

READ

CONTROL

RESET

LOGIC

FLAG

LOGIC

FL RT

EXPANSION

LOGIC

XO HF

3140 drw 01

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

DECEMBER 1996

DSC-3140/2

5.05

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

GND

P28-1

D28-1

Vcc

FL/RT

XO/HF

INDEX

3140 drw 02

Vcc

PIN CONFIGURATIONS

J32-1

L32-1

XO HF

3140 drw 03

DIP

TOP VIEW

PLCC/LCC

TOP VIEW

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

TERM

Rating

Terminal

Voltage with

Respect to

GND

Operating

Temperature

Under Bias

Storage

Temperature

DC Output

Current

Commercial

–0.5 to + 7.0

Military

–0.5 to +7.0

Unit

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

CCM

CCC

GND

(1)

Parameter

Military Supply

Voltage

Commercial Supply

Voltage

Supply Voltage

Input High Voltage

Commercial

Input High Voltage

Military

Input Low Voltage

Commercial and

Military

Min.

4.5

2.0

2.2

—

Typ.

5.0

—

Max.

5.5

—

0.8

Unit

BIAS

STG

OUT

0 to +70

–55 to +125

–55 to + 125

–55 to +125

–65 to +135

–65 to +155

NOTE:

3140 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

3140 tbl 02

DC ELECTRICAL CHARACTERISTICS FOR THE 7207

(Commercial: V

= 5.0V±10%, T

= 0°C to +70°C; Military: V

= 5.0V±10%, T

= –55°C to +125°C)

IDT7207

Commercial

= 15, 20, 25, 35, 50 ns

Symbol

LI(1)

LO(2)

CC1(3)

CC2(3)

CC3

(L)

(3)

IDT7207

Military

= 20, 30, 50 ns

Min.

–1

–10

2.4

—

Typ.

—

Max.

—

0.4

150

(4)

Parameter

Input Leakage Current (Any Input)

Output Leakage Current

Output Logic “1” Voltage I

= –2mA

Output Logic “0” Voltage I

= 8mA

Active Power Supply Current

Standby Current (

)

Power Down Current (All Input = V

- 0.2V)

Min.

–1

–10

2.4

—

Typ.

—

Max.

—

0.4

120

(4)

Unit

µA

3140 tbl 04

NOTES:

1. Measurements with 0.4

≤

2. R

≥

, 0.4

≤

OUT

≤

3. I

measurements are made with outputs open (only capacitive loading).

4. Tested at f = 20MHz.

5.05

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: V

= 5V

10%, T

= 0°C to +70°C; Military: V

= 5V

10%, T

= –55°C to +125°C)

Com'l

7207L15

Symbol

tRC

tRR

tRPW

tRLZ

tWLZ

tDV

tRHZ

tWC

tWPW

tWR

tDS

tDH

tRSC

tRS

tRSS

tRTR

tRTC

tRT

tRTS

tRSR

tEFL

tRTF

tREF

tRFF

tRPE

tWEF

tWFF

tWHF

tRHF

tWPF

tXOL

tXOH

tXI

tXIR

tXIS

Parameters

Shift Frequency

Read Cycle Time

Access Time

Read Recovery Time

Read Pulse Width

(2)

Com'l & Mil.

7207L20

—

33.3

—

Com'l

7207L25

—

28.5

—

Military

7207L30

—

Com'l

7207L35

—

22.2

—

Com'l & Mil.

7207L50

Min. Max. Unit

—

MHz

3140 tbl 05

Min.

—

(3)

Max. Min. Max. Min. Max. Min. Max. Min. Max.

—

Read LOW to Data Bus LOW

(3)

Write HIGH to Data Bus Low-Z

(3, 4)

Data Valid from Read HIGH

Read HIGH to Data Bus High-Z

Write Cycle Time

Write Pulse Width

(2)

Write Recovery Time

Data Set-up Time

Data Hold Time

Reset Cycle Time

Reset Pulse Width

(2)

Reset Set-up Time

(3)

Reset Recovery Time

Retransmit Cycle Time

Retransmit Pulse Width

(2)

Retransmit Set-up Time

(3)

Retransmit Recovery Time

Reset to EF LOW

Retransmit LOW to Flags Valid

Read LOW to EF LOW

Read HIGH to FF HIGH

Read Pulse Width after EF HIGH

Write HIGH to EF HIGH

Write LOW to FF LOW

Write LOW to HF Flag LOW

Read HIGH to HF Flag HIGH

Write Pulse Width after FF HIGH

Read/Write LOW to XO LOW

Read/Write HIGH to XO HIGH

XI Pulse Width

(2)

XI Recovery Time

XI Set-up Time

—

tHFH, tFFH Reset to HF and FF HIGH

NOTES:

1. Timings referenced as in AC Test Conditions.

2. Pulse widths less than minimum are not allowed.

3. Values guaranteed by design, not currently tested.

4. Only applies to read data flow-through mode.

5.05

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns

1.5V

See Figure 1

3140

bl 07

1.1KΩ

D.U.T.

680Ω

30pF*

CAPACITANCE

(1)

= +25°C, f = 1.0 MHz)

Symbol

(1)

OUT

(1,2)

Parameter

Input Capacitance

Output Capacitance

Condition

= 0V

OUT

= 0V

Max.

Unit

3140

bl 08

OR EQUIVALENT CIRCUIT

3140 drw 04

NOTES:

1. This parameter is sampled and not 100% tested.

2. With output deselected.

Figure 1. Output Load

*Includes jig and scope capacitances.

SIGNAL DESCRIPTIONS

Inputs:

DATA IN (D

–D

)

— Data inputs for 9-bit wide data.

Controls:

RESET (

) —

Reset is accomplished whenever the Reset

(

) input is taken to a LOW state. During reset, both internal

read and write pointers are set to the first location. A reset is

required after power-up before a write operation can take place.

Both the Read Enable (

) and Write Enable (

) inputs must

be in the HIGH state during the window shown in Figure 2

(i.e. t

RSS

before the rising edge of

) and should not

change until t

RSR

after the rising edge of

WRITE ENABLE (

) —

A write cycle is initiated on the falling

edge of this input if the Full Flag (

) is not set. Data set-up and

hold times must be adhered-to, with respect to the rising edge

of the Write Enable (

). Data is stored in the RAM array

sequentially and independently of any on-going read operation.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (

) will be set to LOW,

and will remain set until the difference between the write pointer

and read pointer is less-than or equal to one-half of the total

memory of the device. The Half-Full Flag (

) is reset by the

rising edge of the read operation.

To prevent data overflow, the Full Flag (

) will go LOW on

the falling edge of the last write signal, which inhibits further write

operations. Upon the completion of a valid read operation, the

Full Flag (

) will go HIGH after t

RFF

, allowing a new valid write

to begin. When the FIFO is full, the internal write pointer is

blocked from

, so external changes in

will not affect the FIFO

when it is full.

READ ENABLE (

) —

A read cycle is initiated on the falling

edge of the Read Enable (

), provided the Empty Flag (

) is not

set. The data is accessed on a First-In/First-Out basis, inde-

pendent of any ongoing write operations. After Read Enable (

)

goes HIGH, the Data Outputs (Q

through Q

) will return to a

high-impedance condition until the next Read operation. When

all the data has been read from the FIFO, the Empty Flag (

)

will go LOW, allowing the “final” read cycle but inhibiting further

read operations, with the data outputs remaining in a high-

impedance state. Once a valid write operation has been accom-

plished, the Empty Flag (

) will go HIGH after t

WEF

and a valid

Read can then begin. When the FIFO is empty, the internal read

pointer is blocked from

so external changes will not affect the

FIFO when it is empty.

FIRST LOAD/RETRANSMIT (

) —

This is a dual-

purpose input. In the Depth Expansion Mode, this pin is

grounded to indicate that it is the first device loaded (see

Operating Modes). The Single Device Mode is initiated by

grounding the Expansion In (

The IDT7207 can be made to retransmit data when the

Retransmit Enable Control (

) input is pulsed LOW. A retrans-

mit operation will set the internal read pointer to the first location

and will not affect the write pointer. The status of the Flags will

change depending on the relative locations of the read and write

pointers. Read Enable (

) and Write Enable (

) must be in the

HIGH state during retransmit. This feature is useful when less

than 32,768 writes are performed between resets. The retrans-

mit feature is not compatible with the Depth Expansion Mode.

EXPANSION IN (

)

— This input is a dual-purpose pin.

Expansion In (

) is grounded to indicate an operation in the

single device mode. Expansion In (

) is connected to Expan-

sion Out (

) of the previous device in the Depth Expansion or

Daisy-Chain Mode.

5.05

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Outputs:

FULL FLAG (

)

— The Full Flag (

) will go LOW, inhibiting

further write operations, when the device is full. If the read

pointer is not moved after Reset (

), the Full Flag (

) will go

LOW after 32,768 writes.

EMPTY FLAG (

)

— The Empty Flag (

) will go LOW,

inhibiting further read operations, when the read pointer is equal

to the write pointer, indicating that the device is empty.

EXPANSION OUT/HALF-FULL FLAG (

) —

This is a

dual-purpose output. In the single device mode, when Expan-

sion In (

) is grounded, this output acts as an indication of a half-

full memory.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (

) will be set to LOW

and will remain set until the difference between the write pointer

and read pointer is less than or equal to one half of the total

memory of the device. The Half-Full Flag (

) is then reset by

the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (

) is con-

nected to Expansion Out (

) of the previous device. This

output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device

reaches the last location of memory. There will be an

pulse

when the Write pointer reaches the last location of memory, and

an additional

pulse when the Read pointer reaches the last

location of memory.

DATA OUTPUTS (Q

-Q

) —

-Q

are data outputs for 9-

bit wide data. These outputs are in a high-impedance condition

whenever Read (

) is in a HIGH state.

RSC

RSS

RSR

RSS

EFL

HFH

, t

FFH

HF FF

3140 drw 05

NOTE:

and

= V

around the rising edge of

Figure 2. Reset

RPW

DATA

OUT

RLZ

–Q

RHZ

DATA

OUT

VALID

WPW

–D

DATA

VALID

DATA

VALID

3140 drw 06

Figure 3. Asynchronous Write and Read Operation

5.05