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IDT7216L185LC

Multiplier, CMOS, CQCC68

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
Reach Compliance Code
_compli
JESD-30 代码
S-XQCC-N68
JESD-609代码
e0
端子数量
68
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
CERAMIC
封装代码
QCCN
封装等效代码
LCC68,.95SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
峰值回流温度(摄氏度)
260
电源
5 V
认证状态
Not Qualified
标称供电电压
5 V
表面贴装
YES
技术
CMOS
温度等级
MILITARY
端子面层
Tin/Lead (Sn/Pb)
端子形式
NO LEAD
端子节距
1.27 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
6
uPs/uCs/外围集成电路类型
DSP PERIPHERAL, MULTIPLIER
Base Number Matches
1
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IDT7216L
16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
16-BIT PARALLEL
CMOS MULTIPLIERS
IDT7216L
FEATURES:
16 x 16 parallel multiplier with double precision product
16ns clocked multiply time
Low power consumption: 120mA
Produced with advanced submicron CMOS high performance
technology
IDT7216L is pin- and function compatible with TRW MPY016H/K
and AMD Am29516
Configured for easy array expansion
User-controlled option for transparent output register mode
Round control for rounding the MSP
Input and output directly TTL-compatible
Three-state output
Available in PLCC
Speeds available: L16/20/25/35/45/55/65
DESCRIPTION:
The IDT7216 is a high-speed, low-power 16 x 16-bit multiplier, ideal
for fast, real time digital signal processing applications. Utilization of a
modified Booths algorithm and IDT’s high-performance, submicron CMOS
technology, has achieved speeds comparable to bipolar (20ns max.), at 1/
10 the power consumption.
The IDT7216 is ideal for applications requiring high-speed multiplication
such as fast Fourier transform analysis, digital filtering, graphic display
systems, speech synthesis and recognition and in any system requirement
where multiplication speeds of a mini/microcomputer are inadequate.
All input registers, as well as LSP and MSP output registers, use the same
positive edge-triggered D-type flip-flop. In the IDT7216, there are indepen-
dent clocks (CLKX, CLKY, CLKM, CLKL) associated with each of these
registers.
The IDT7216 offers additional flexibility with the FA control and
MSPSEL
functions. The FA control formats the output for two’s complement by shifting
the MSP up one bit and then repeating the sign bit in the MSB of the LSP.
The
MSPSEL
low selects the MSP to be available at the product output port,
while a high selects the LSP to be available. Keeping this pin low will ensure
compatibility with the TRW MPY016H.
FUNCTIONAL BLOCK DIAGRAM
X
M
X
15
-
0
RND
Y
M
Y
15
-
0
/P
15
-
16
0
16
XREGISTER
CLKX
CLKY
REGISTER
YREGISTER
OEL
MULTIPLIER
ARRAY
FA
FORMAT ADJUST
MSP
REGISTER
LSP
REGISTER
FT
CLKM
CLKL
16
16
MSPSEL
OEP
MULTIPLEXER
PRODUCT
16
MSP
O U T
(P
31
- P
16
)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2001 Integrated Device Technology, Inc.
SEPTEMBER 2001
DSC-5746/1
IDT7216L
16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
X
12
X
11
NC
X
10
CLKY
44
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
X
0
46
OEL
45
X
13
X
14
X
15
CLKX
RND
X
M
Y
M
Vcc
Vcc
GND
GND
MSPSEL
FA
FT
OEP
CLKM
NC
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
CLKL
43
42
41
40
39
38
37
NC
P
0
,Y
0
P
1
,Y
1
P
2
,Y
2
P
3
,Y
3
P
4
,Y
4
P
5
,Y
5
P
6
,Y
6
P
7
,Y
7
P
8
,Y
8
P
9
,Y
9
P
10
,Y
10
P
11
,Y
11
P
12
,Y
12
P
13
,Y
13
P
14
,Y
14
P
15
,Y
15
J68-1
36
35
34
33
32
31
30
29
28
27
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P
9
,P
25
P
8
,P
24
P
7
,P
23
P
6
,P
22
P
5
,P
21
P
4
,P
20
P
3
,P
19
P
15
,P
31
P
14
,P
30
P
13
,P
29
P
12
,P
28
P
11
,P
27
P
10
,P
26
P
2
,P
18
P
1
,P
17
P
0
,P
16
PLCC
TOP VIEW
2
NC
IDT7216L
16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
TERM
T
A
T
BIAS
T
STG
I
OUT
Description
Power Supply Voltage
Terminal Voltage with Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current
Max
–0.5 to +7
V
CC
+ 0.5
0 to +70
–55 to +125
–55 to +125
50
Unit
V
V
°C
°C
°C
mA
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name
X
0
- X
15
Y
0 -
Y
15
/
P
0
- P
15
P
16
- P
31
OEL
OEP
X
M,
Y
M
RND
O
I
I
I
I
I/O
I
I/O
Data Inputs
Y
0 -
Y
15
are data inputs
P
0
- P
15
are LSP register output, enabled when
OEL
= 0
Data Output (LSP or MSP)
Output enable control for LSP (least significant product). When LOW enables P
0
- P
15
. When HIGH P
0
- P
15
tristated.
Output enable control for MSP (most significant product). When LOW enables P
16
- P
31.
When HIGH P
16
- P
31
tristated.
Mode control for each data word. LOW designates unsigned data input and HIGH designates two’s complement.
“Round” control for rounding of MSP. When HIGH, 1 is added to the most significant bit of LSP. This signal is affected by the state of FA pin.
When FA = 1 and RND = 1, 1 is added to the 2
-15
bit (P
15
). When RND = 1 and FA = 0, 1 is added to the 2
-16
bit (P
14
). The RND input is
registered. It is clocked on the rising edge of the logical OR of CLKX and CLKY. Rounding always occurs in the positive direction which may
introduce a systematic bias.
MSPSEL
FA
FT
CLKX
CLKY
CLKL
CLKM
I
I
I
I
I
I
I
When LOW, MSP is output on P
16
- P
31
lines. When HIGH, LSP is output on P
16
- P
31.
Format adjust control. When HIGH, a full 32 bit product is selected. When LOW, a left shifted 31 bit product is selected with the sign bit
replicated in the LSP. FA is normally HIGH, except for certain fractional two’s complement applications (see multiplier input / output formats).
Flow through control. When HIGH, both MSP and LSP registers are by-passed.
X register clock input. Also clocks RND register.
Y register clock input. Also clocks RND register.
LSP register clock input.
MSP register clock input.
Description
3
IDT7216L
16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5V ± 10%
Symbol
V
IH
V
IL
I
LI
I
LO
I
CC
I
CCQ1
I
CCQ2
I
CC
/f
(2,3)
V
OH
V
OL(4)
I
OS
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Quiescent Power Supply Current
Quiescent Power Supply Current
Increase in Power Supply Current
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max., V
IN
= 0 to V
CC
V
CC
= Max.,
OE
= 2V, V
OUT
= 0 to V
CC
V
CC
= Max., Outputs Disabled, f = 10MHz
(2)
V
IN
V
IH,
V
IN
V
IL
V
IN
V
CC
- 0.2V, V
IN
0.2V
V
CC
= Max., Outputs Disabled
V
CC
= Min., I
OH
= –2mA
V
CC
= Min., I
OL
= 8mA
V
CC
= Max., V
O
= GND
Min.
2
2.4
-20
Typ.
(1)
40
20
4
Max.
0.8
10
10
80
40
20
4
0.4
-120
Unit
V
V
µA
µA
mA
mA
mA
mA/MHz
V
V
mA
NOTES:
1. Typical implies V
CC
= 5V and T
A
= +25°C.
2. I
CC
is measured at 10MHz and V
IN
= 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
I
CC
= 80+ 4(f –10)mA; for the military range, I
CC
= 100 + 6(f –10). f = operating frequency in MHz and f = 1/t
MC
.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. I
OL
= 4mA for t
MC
>65ns.
4
IDT7216L
16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5V ± 10%
7216L16
Symbol
t
MUC
t
MC
t
S
t
H
t
PWH
t
PWL
t
PDSEL
t
PDP
t
PDY
t
ENA
t
DIS
t
HCL
Parameter
Unclocked Multiply Time
(4)
Clocked Multiply Time
(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
MSPSEL
to Product Out
(4)
Output Clock to P
(4)
Output Clock to Y
(4)
3-State Enable Time
3-State Disable Time
(2)
Clock LOW Hold Time CLKXY Relative to CLKML
(1,3)
Min.
2
2
10
1
7
7
2
2
2
0
Max.
25
16
15
15
15
15
15
2
2
11
1
9
9
2
2
2
0
7216L20
Min.
Max.
30
20
18
18
18
18
18
7216L25
Min.
2
2
12
2
10
10
2
2
2
0
Max.
38
25
20
20
20
20
20
7216L35
Min.
2
2
12
3
10
10
2
2
2
0
Max.
55
35
25
25
25
25
22
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7216L45
Symbol
t
MUC
t
MC
t
S
t
H
t
PWH
t
PWL
t
PDSEL
t
PDP
t
PDY
t
ENA
t
DIS
t
HCL
Parameter
Unclocked Multiply Time
(4)
Clocked Multiply Time
(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
MSPSEL
to Product Out
(4)
Output Clock to P
(4)
Output Clock to Y
(4)
3-State Enable Time
3-State Disable Time
(2)
Clock LOW Hold Time CLKXY Relative to CLKML
(1,3)
Min.
2
2
15
3
15
15
2
2
2
0
Max.
65
45
25
25
25
25
22
7216L55
Min.
2
2
20
3
15
20
2
2
2
0
Max.
75
55
25
30
30
30
25
7216L65
Min.
2
2
20
3
15
20
2
2
2
0
Max.
85
65
30
30
30
35
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
5
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