CMOS SyncFIFO™
256 x 18, 512 x 18, 1024 x 18, 2048 x
18 and 4096 x 18
Integrated Device Technology, Inc.
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
256 x 18-bit organization array (72205LB)
512 x 18-bit organization array (72215LB)
1024 x 18-bit organization array (72225LB)
2048 x 18-bit organization array (72235LB)
4096 x 18-bit organization array (72245LB)
15 ns read/write cycle time
Easily expandable in depth and width
Read and write clocks can be asynchronous or coincident
Dual-Port zero fall-through time architecture
Programmable almost-empty and almost-full flags
Empty and Full flags signal FIFO status
Half-Full flag capability in a single device configuration
Output enable puts output data bus in high-impedance
state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP),
pin grid array (PGA), and plastic leaded chip carrier
(PLCC)
Military product compliant to MIL-STD-883, Class B
Industrial temperature range (-40
O
C to +85
O
C) is avail-
able, tested to military electrical specifications
•
•
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs
are applicable for a wide variety of data buffering needs, such
as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
Both FIFOs have 18-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a data
input enable pin (
WEN
). Data is read into the synchronous
FIFO on every clock when
WEN
is asserted. The output port
is controlled by another clock pin (RCLK) and another enable
pin (
REN
). The read clock can be tied to the write clock for
single clock operation or the two clocks can run asynchronous
of one another for dual-clock operation. An Output Enable pin
(
OE
) is provided on the read port for three-state control of the
output.
The synchronous FIFOs have two fixed flags, Empty (
EF
)
and Full (
FF
), and two programmable flags, Almost-Empty
(
PAE
) and Almost-Full (
PAF
). The offset loading of the pro-
grammable flags is controlled by a simple state machine, and
is initiated by asserting the Load pin (
LD
). A Half-Full flag (
HF
)
is available when the FIFO is used in a single device configu-
ration.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
are depth expandable using a daisy-chain technique. The XI
and
XO
pins are used to expand the FIFOs. In depth expan-
sion configuration, FL is grounded on the first device and set
to HIGH for all other devices in the daisy chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is
fabricated using IDT’s high-speed submicron CMOS technol-
ogy. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D0-D17
LD
OFFSET REGISTER
INPUT REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
FL
WXI
(
HF
)/
WXO
RXI
RXO
RS
•
•
RAM ARRAY
256 x 18, 512 x 18
1024 x 18, 2048 x 18
4096 x 18
•
•
FLAG
LOGIC
FF
PAF
EF
PAE
HF
/(
WXO
)
READ POINTER
READ CONTROL
LOGIC
EXPANSION LOGIC
OUTPUT REGISTER
RESET LOGIC
OE
Q0-Q17
RCLK
REN
2766 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2766/7
5.16
1
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
11
V
CC
Q
3
GND Q
0
Q
2
Q
1
10 GND Q
4
09
08
Q
6
Q
7
Q
5
V
CC
WXO
/
RXI
V
CC
WEN FL
HF
RXO FF PAF WXI
WCLK
PAE
D
2
D
4
D
6
G68-1
D
0
D
1
D
3
D
5
07 GND Q
8
06
05
Q
10
Q
9
GND D
7
V
CC
D
8
Q
11
V
CC
Pin 1 Designator
04 GND Q
12
03
02
01
A
Q
14
Q
13
D
10
D
9
D
12
D
11
V
CC
Q
15
Q
16
V
CC
GND
GND Q
17
B
C
RS LD
OE REN
F
G
RCLK
D
17
D
14
D
13
EF
D
V
CC
E
GND D
16
D
15
H
J
K
L
PGA
TOP VIEW
2766 drw 02
D
15
D
16
D
17
GND
RCLK
V
CC
GND
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
9 8 7 6 5 4 3 2
68 67 66 65 64 63 62 61
10
60
1
11
59
12
58
13
57
14
56
15
55
16
54
17
53
J68-1
18
52
19
51
20
50
49
21
48
22
47
23
46
24
45
25
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V
CC
Q
17
Q
16
GND
Q
15
V
CC
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
Q
6
Q
5
GND
Q
4
2766 drw 03
REN
LD
OE
RS
V
CC
5.16
WEN
WXI
WCLK
PAF
RXI
FF
WXO
/
HF
RXO
PLCC
TOP VIEW
Q
0
Q
1
GND
Q
2
Q
3
V
CC
PAE
FL
EF
2
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
RCLK
GND
GND
REN
LD
OE
RS
GND
V
CC
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
PN 64-1
41
8
PP64-1
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
PAF
RXI
FF
WXO
/
HF
RXO
PAE
FL
WEN
WXI
V
CC
GND
Q
0
Q
1
WCLK
Q
2
Q
3
V
CC
D
17
Q
17
Q
16
D
16
Q
15
EF
2766 drw 04
TQFP/STQFP
TOP VIEW
NOTE:
1. For information on the flatpack (F68-1), contact factory.
5.16
3
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D0–D17
Name
Data Inputs
Reset
I/O
I
I
Data inputs for a 18-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the
RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an
initial WRITE after power-up.
When
WEN
is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,
if the FIFO is not full.
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of
WCLK. When
WEN
is HIGH, the FIFO holds the previous data. Data will not be written
into the FIFO if the
FF
is LOW.
Description
RS
WCLK
Write Clock
Write Enable
I
I
WEN
RCLK
Read Clock
Read Enable
I
I
When
REN
is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if
the FIFO is not empty.
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of
RCLK. When
REN
is HIGH, the output register holds the previous data. Data will not be
read from the FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will
be in a high-impedance state.
REN
OE
LD
Output Enable
Load
I
I
FL
WXI
RXI
EF
PAE
PAF
FF
WXO
/
HF
RXO
Q0–Q17
VCC
GND
First Load
I
In the single device or width expansion configuration,
FL
is grounded. In the depth
expansion configuration,
FL
is grounded on the first device (first load device) and set to
HIGH for all other devices in the daisy chain.
In the single device or width expansion configuration,
WXI
is grounded. In the depth
expansion configuration,
WXI
is connected to
WXO
(Write Expansion Out) of the
previous device.
When
LD
is LOW, data on the inputs D0–D11 is written to the offset and depth registers
on the LOW-to-HIGH transition of the WCLK, when
WEN
is LOW. When
LD
is LOW,
data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-to-
HIGH transition of the RCLK, when
REN
is LOW.
Write Expansion
Input
Read Expansion
Input
Empty Flag
I
I
In the single device or width expansion configuration, RXI is grounded. In the depth
expansion configuration,
RXI
is connected to
RXO
(Read Expansion Out) of the previous
device.
When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited.
When
EF
is HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
When
PAE
is LOW, the FIFO is almost empty based on the offset programmed into the
FIFO. The default offset at reset is 31 from empty for 72205LB, 63 from empty for
72215LB, and 127 from empty for 72225LB/72235LB/72245LB.
O
Programmable
O
Almost-Empty Flag
Programmable
O
When
PAF
is LOW, the FIFO is almost full based on the offset programmed into the FIFO.
The default offset at reset is 31 from full for 72205LB, 63 from full for 72215LB, and
127 from full for 72225LB/72235LB/72245LB.
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited.
When
FF
is HIGH, the FIFO is not full.
FF
is synchronized to WCLK.
In the single device or width expansion configuration, the device is more than half full
when
HF
is LOW. In the depth expansion configuration, a pulse is sent from
WXO
to
WXI
of the next device when the last location in the FIFO is written.
Full Flag
Write Expansion
Out/Half-Full Flag
Read Expansion
Out
Data Outputs
Power
Ground
O
O
O
O
In the depth expansion configuration, a pulse is sent from
RXO
to
RXI
of the next device
when the last location in the FIFO is read.
Data outputs for a 18-bit bus.
Eight +5V power supply pins for the PLCC and PGA, five pins for the TQFP.
Eight ground pins for the PLCC and PGA, seven pins for the TQFP.
2766 tbl 01
5.16
4
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
Rating
Commercial
MIilitary
–0.5 to +7.0
–55 to +125
–65 to +135
–65 to +155
50
Unit
V
°C
Terminal Voltage
–0.5 to +7.0
with respect to GND
Operating
Temperature
0 to +70
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CCM
V
CCC
Parameter
Military Supply
Voltage
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
Min.
4.5
4.5
0
2.0
2.2
—
Typ.
5.0
5.0
0
—
—
—
Max.
5.5
5.5
0
—
—
0.8
Unit
V
V
V
V
V
V
Temperature Under –55 to +125
Bias
Storage
Temperature
DC Output Current
–55 to +125
50
°C
GND
°C
mA
V
IH
V
IH
V
IL
(1)
NOTE:
2766 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maimum rating conditions for extended
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2766 tbl 03
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
IDT72205LB
IDT72215LB
IDT72225LB
Commercial
t
CLK
= 15, 20, 25, 35, 50ns
Symbol
ILI
(1)
ILO
(2)
VOH
VOL
ICC1
(3)
ICC2
(3)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
Average Standby Current (All Input = VCC – 0.2V,
except RCLK and WCLK which are free-running)
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
1
10
—
0.4
200
70
IDT72205LB
IDT72215LB
IDT72225LB
Military
t
CLK
= 25, 35, 50ns
Min.
–10
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
10
10
—
0.4
250
85
Unit
µA
µA
V
V
mA
mA
IDT72235LB
IDT72245LB
Commercial
t
CLK
= 15, 20, 25, 35, 50ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(4)
I
CC2(4)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Average Standby Current (All Input = V
CC
– 0.2V,
except RCLK and WCLK which are free-running)
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
1
10
—
0.4
200
70
IDT72235LB
IDT72245LB
Military
t
CLK
= 25, 35, 50ns
Min.
–10
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
10
10
—
0.4
250
85
Unit
µA
µA
V
V
mA
mA
2766 tbl 04
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
OE
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
3 & 4. Tested at f = 20MHz with outputs unloaded.
(3) Typical Icc
1
= 60 + (f
CLK*
0.57/MHz) + (f
CLK
*C
L
*0.02/MHz-pF) mA
(4 ) Typical Icc
1
= 80 + (f
CLK
+ 0.73/MHz) + (f
CLK
*C
L
*0.02/MHz-pF) mA
f
CLK
= 1/t
CLK
, C
L
= external capacitive load (30 pF typical)
5.16
5
