2.5V 18M-BIT HIGH-SPEED TeraSync
TM
FIFO 36-BIT CONFIGURATIONS
524,288 x 36
IDT72T36135M
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FEATURES:
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Industry’s largest FIFO memory organization:
IDT72T36135
524,288 x 36 - 18M-bits
Up to 200 MHz Operation of Clocks
Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync
devices
User selectable HSTL/LVTTL Input and/or Output
User selectable Asynchronous read and/or write port timing
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input disables Write Port
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty and Full flags signal FIFO status
Select IDT Standard timing (using
EF[1:2]
and
FF[1:2]
flags) or First
Word Fall Through timing (using
OR[1:2]
and
IR[1:2]
flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
50% more space saving than the leading 9M-bit FIFOs
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
D
0
-D
n
(x36)
WEN
WCLK/WR
WCS
LD
SEN
SCLK
INPUT REGISTER
OFFSET REGISTER
FF/IR[1:2]
PAF[1:2]
EF/OR[1:2]
PAE[1:2]
FWFT/SI
PFM
FSEL0
FSEL1
ASYW
WRITE CONTROL
LOGIC
FLAG
LOGIC
RAM ARRAY
524,288 x 36
READ POINTER
WRITE POINTER
MRS
PRS
TCK
TRST
TMS
TDO
TDI
Vref
WHSTL
RHSTL
SHSTL
RESET
LOGIC
JTAG CONTROL
(BOUNDARY
SCAN)
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
MARK
ASYR
HSTL I/0
CONTROL
RCLK/RD
REN
RCS
OE
6723 drw01
Q
0
-Q
n
(x36)
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2006
DSC-6723/3
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO
524,288 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
A1 BALL PAD CORNER
A
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
WCLK
PRS
GND
FF1
FF2
RCLK
OE
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
B
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
WEN
MRS
GND
PAF1
EF1
REN
RCS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
C
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
WCS
LD
GND
PAF2 PAE1
MARK
RT
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
D
V
CC
V
CC
V
CC
FWFT/SI DNC
FSEL0 SHSTL
FSEL1 GND
GND
PAE2
EF2
RHSTL
ASYR
PFM
V
DDQ
V
DDQ
V
DDQ
E
V
CC
V
CC
V
CC
GND
GND
V
DDQ
V
DDQ
V
DDQ
F
V
CC
V
CC
V
CC
GND
GND
V
DDQ
V
DDQ
V
DDQ
G
V
CC
SEN
SCLK
WHSTL
GND
V
DDQ
V
DDQ
V
DDQ
H
V
CC
V
CC
V
CC
ASYW
GND
GND
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
J
V
CC
V
CC
V
CC
VREF
GND
GND
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
K
V
CC
V
CC
V
CC
DNC
GND
GND
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
L
D33
D34
D35
GND
GND
GND
GND
GND
GND
V
DDQ
Q35
Q34
M
D30
D31
D32
GND
GND
Q33
Q32
Q31
N
D27
D28
D29
GND
GND
Q30
Q29
Q28
P
D24
D25
D26
GND
GND
Q27
Q26
Q25
R
D21
D22
D23
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Q24
Q23
Q22
T
D19
D20
D13
D10
D5
D4
D1
TMS
TDO
GND
Q0
Q2
Q3
Q8
Q11
Q14
Q21
Q20
U
D18
D17
D14
D11
D7
D8
D2
TRST
TDI
GND
Q1
Q6
Q5
Q9
Q12
Q15
Q18
Q19
V
V
CC
D16
D15
D12
D9
D6
D3
D0
TCK
GND
DNC
Q4
Q7
Q10
Q13
Q16
Q17
V
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
6723 drw02
NOTE:
1. DNC - Do Not Connect.
PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB)
TOP VIEW
2
MAY 29, 2006
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO
524,288 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72T36135M is an exceptionally deep, extrememly high speed,
CMOS First-In-First-Out (FIFO) memoriy with clocked read and write controls
and a wide extended x36 bus to allow ample data flow. These FIFOs offer
several key user benefits:
•
High density offering of 18 Mbit
•
200MHz R/W Clocks supporting 7.2Gbps of data throughput
•
User selectable MARK location for retransmit
•
User selectable I/O structure for HSTL or LVTTL
•
Asynchronous/Synchronous translation on the read or write ports
•
The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is fixed and short.
TeraSync FIFOs are particularly appropriate for network, video, telecom-
munications, data communications and other applications that need to buffer
large amounts of data at very high performance.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when
WEN
is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the
WEN
input should be tied to its active state, (LOW).
The input port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the WHSTL input during a master reset.
A Write Chip Select input (WCS) is provided for use when the write port is in
both LVTTL and HSTL modes. During operation the
WCS
input can be used
to disable write port inputs (data only).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when
REN
is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the
REN
input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, also the
RCS
should be
tied LOW and the
OE
input used to provide three-state control of the outputs, Qn.
The output port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the RHSTL input during a master reset.
An Output Enable (OE) input is provided for three-state control of the outputs.
A Read Chip Select (RCS) input is also provided, the
RCS
input is synchronized
to the read clock, and also provides three-state control of the Qn data outputs.
When
RCS
is disabled, the data outputs will be high impedance. During
Asynchronous operation of the output port,
RCS
should be enabled, held LOW.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to f
MAX
with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In
IDT Standard mode,
the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
REN
and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In
FWFT mode,
the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on
REN
for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
3
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
The 18M-bit TeraSync FIFO has 8 flag pins,
EF/OR[1:2]
(Empty Flag or
Output Ready),
FF/IR[1:2]
(Full Flag or Input Ready),
PAE[1:2]
(Program-
mable Almost-Empty flag) and
PAF[1:2]
(Programmable Almost-Full flag). The
EF[1:2]
and
FF[1:2]
functions are selected in IDT Standard mode. The
IR[1:2]
and
OR[1:2]
functions are selected in FWFT mode.
PAE[1:2]
and
PAF[1:2]
are
always available for use, irrespective of timing mode. Each flag has a double
because the 18M FIFO was designed as a Multi-chip Module, so each set of
flags supports its respective internal 9M FIFO. Some extra external gating logic
will have to be used to accurately read each flag output. This will be covered
in the flagging section of the datasheet.
PAE[1:2]
and
PAF[1:2]
can be programmed independently to switch at any
point in memory. Programmable offsets determine the flag switching threshold
and can be loaded by two methods: parallel or serial. Eight default offset settings
are also provided, so that
PAE[1:2]
can be set to switch at a predefined number
of locations from the empty boundary and the
PAF[1:2]
threshold can also be
set at similar predefined values from the full boundary. The default offset values
are set during Master Reset by the state of the FSEL0, FSEL1, and
LD
pins.
For serial programming,
SEN
together with
LD
on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming,
WEN
together with
LD
on each rising edge of WCLK, are used
to load the offset registers via D
n
.
REN
together with
LD
on each rising edge
of RCLK can be used to read the offsets in parallel from Q
n
regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect.
PRS
is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the
PAE[1:2]
(Programmable
Almost-Empty flag) and
PAF[1:2]
(Programmable Almost-Full flag) outputs. The
timing modes can be set to be either asynchronous or synchronous for the
PAE[1:2]
and
PAF[1:2]
flags.
If asynchronous
PAE/PAF[1:2]
configuration is selected, the
PAE[1:2]
is
asserted LOW on the LOW-to-HIGH transition of RCLK.
PAE[1:2]
is reset to
HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the
PAF[1:2]
is
asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF[1:2]
is reset
to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous
PAE/PAF[1:2]
configuration is selected , the
PAE[1:2]
is
asserted and updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF[1:2]
is asserted and updated on the rising edge of WCLK only and not
RCLK. The mode desired is configured during MasterReset by the state of the
Programmable Flag Mode (PFM) pin.
This device includes a Retransmit from Mark feature that utilizes two control
inputs, MARK and ,
RT
(Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation,
RT
goes LOW, will reset the read pointer to
this ‘marked’ location.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
MAY 29, 2006
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO
524,288 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture. Special consideration should be taken into
account for JTAG testing since the device is a MCM. Please see JTAG section
for further details.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input HSTL is also provided, this allows the user to
select HSTL operation for other pins on the device (not associated with the write
or read ports).
The IDT72T36135M is fabricated using IDT’s high speed submicron CMOS
technology.
4
MAY 29, 2006
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO
524,288 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PARTIAL RESET (PRS)
MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR)
WRITE ENABLE (WEN)
WRITE CHIP SELECT (WCS)
LOAD (LD)
(x36) DATA IN (D
0
- D
n
)
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
FULL FLAG/INPUT READY (FF/IR[1:2])
PROGRAMMABLE ALMOST-FULL (PAF[1:2])
IDT
72T36135M
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
READ CHIP SELECT (RCS)
(x36) DATA OUT (Q
0
- Q
n
)
RCLK
REN
MARK
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR[1:2])
PROGRAMMABLE ALMOST-EMPTY (PAE[1:2])
6723 drw03
Figure 1. Single Device Configuration Signal Flow Diagram
5
MAY 29, 2006
