3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9, 16,384 x 9
IDT72V01, IDT72V02
IDT72V03, IDT72V04
IDT72V05, IDT72V06
FEATURES:
•
•
•
•
•
•
•
•
•
DESCRIPTION:
The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO
memories that operate at a power supply voltage (Vcc) between 3.0V and 3.6V.
Their architecture, functional operation and pin assignments are identical to
those of the IDT7201/7202/7203/7204/7205/7206. These devices load and
empty data on a first-in/first-out basis. They use Full and Empty flags to prevent
data overflow and underflow and expansion logic to allow for unlimited
expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins. The devices have a maximum data access time as fast as 25 ns.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. They also feature a Retransmit (RT) capability that allows for
reset of the read pointer to its initial position when
RT
is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology. It
has been designed for those applications requiring asynchronous and simul-
taneous read/writes in multiprocessing and rate buffer applications.
•
•
•
•
•
•
•
3.3V family uses less power than the 5 Volt 7201/7202/7203/7204/
7205/7206 family
512 x 9 organization (72V01)
1,024 x 9 organization (72V02)
2,048 x 9 organization (72V03)
4,096 X 9 organization (72V04)
8,192 x 9 organization (72V05)
16,384 X 9 organization (72V06)
Functionally compatible with 720x family
Low-power consumption
— Active: 180 mW (max.)
— Power-down: 18 mW (max.)
15 ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
Available in 32-pin PLCC
Industrial temperature range (–40°C to +85°C) is available
°
°
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D
0-
D
8
)
W
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
16,384 x 9
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q
0-
Q
8
)
RS
RESET
LOGIC
FL/RT
FLAG
LOGIC
EXPANSION
LOGIC
EF
FF
XI
XO/HF
3033 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
DSC-3033/3
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
D
3
D
8
D
5
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Com'l & Ind'l
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
INDEX
W
NC
V
CC
D
4
°
C
mA
4 3 2
1 32 31 30
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
Q
8
GND
NC
R
29
28
27
26
25
24
23
22
21
D
6
D
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
(1)
V
IL
(2)
T
A
T
A
Rating
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature Commercial
Operating Temperature Industrial
Min.
3.0
0
2.0
—
0
–40
Typ. Max.
3.3
3.6
0
0
— V
CC
+0.5
—
0.8
—
—
70
85
Unit
V
V
V
V
Q
3
Q
4
Q
5
3033 drw 02b
°
C
°
C
PLCC (J32-1, order code: J)
TOP VIEW
NOTES:
1. For
RT/RS/XI
input, V
IH
= 2.6V (commercial).
For
RT/RS/XI
input, V
IH
= 2.8V (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V ± 0.3V, T
A
= 0°C to +70°C; Industrial: V
CC
= 3.3V ± 0.3V, T
A
= –40°C to +85°C)
IDT72V01
IDT72V02
IDT72V03
IDT72V04
Commercial & Industrial
(1)
t
A
= 15, 25, 35 ns
Symbol
I
LI
(2)
I
LO
(3)
V
OH
V
OL
I
CC1
(4,5)
I
CC2
(4,6)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage I
OH
= –2mA
Output Logic “0” Voltage I
OL
= 8mA
Active Power Supply Current
Standby Current (R=W=RS=FL/RT=V
IH
)
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
60
5
IDT72V05
IDT72V06
Commercial & Industrial
(1)
t
A
= 15, 25, 35 ns
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
75
5
Unit
µA
µA
V
V
mA
mA
NOTES:
1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4
≤
V
IN
≤
V
CC
.
3.
R
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
4. Tested with outputs open (I
OUT
= 0).
5. Tested at f = 20 MHz.
6. All Inputs = V
CC
- 0.2V or GND + 0.2V.
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Condition
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
NOTE:
1. Characterized values, not currently tested.
2
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: V
CC
= 3.3V ± 0.3V, T
A
= 0°C to +70°C; Industrial: V
CC
= 3.3V ± 0.3V, T
A
= –40°C to +85°C)
Commercial
IDT72V01L15
IDT72V02L15
IDT72V03L15
IDT72V04L15
IDT72V05L15
IDT72V06L15
Min.
Max.
—
40
25
—
—
15
10
—
15
—
3
—
5
—
5
—
—
15
25
—
15
—
10
—
11
—
0
—
25
—
15
—
15
—
10
—
25
—
15
—
15
—
10
—
—
25
—
25
—
25
—
15
—
15
15
—
—
15
—
15
—
25
—
25
15
—
—
15
—
15
15
—
10
—
10
—
Com'l and Ind'l
(2)
IDT72V01L25
IDT72V02L25
IDT72V03L25
IDT72V04L25
IDT72V05L25
IDT72V06L25
Min.
Max.
—
28.5
35
—
—
25
10
—
25
—
3
—
5
—
5
—
—
18
35
—
25
—
10
—
15
—
0
—
35
—
25
—
25
—
10
—
35
—
25
—
25
—
10
—
—
35
—
35
—
35
—
25
—
25
25
—
—
25
—
25
—
35
—
35
25
—
—
25
—
25
25
—
10
—
10
—
Commercial
IDT72V01L35
IDT72V02L35
IDT72V03L35
IDT72V04L35
IDT72V05L35
IDT72V06L35
Min.
Max.
—
22.2
45
—
—
35
10
—
35
—
3
—
5
—
5
—
—
20
45
—
35
—
10
—
18
—
0
—
45
—
35
—
35
—
10
—
45
—
35
—
35
—
10
—
—
45
—
45
—
45
—
30
—
30
35
—
—
30
—
30
—
45
—
45
35
—
—
35
—
35
35
—
10
—
10
—
Symbol
f
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RSR
t
RTC
t
RT
t
RTS
t
RTR
t
EFL
t
HFH,FFH
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
Parameter
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
(3)
Read Pulse Low to Data Bus at Low Z
(4)
Write Pulse High to Data Bus at Low Z
(4,5)
Data Valid from Read Pulse High
Read Pulse High to Data Bus at High Z
(4)
Write Cycle Time
Write Pulse Width
(3)
Write Recovery Time
Data Setup Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(3)
Reset Setup Time
(4)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(3)
Retransmit Setup Time
(4)
Retransmit Recovery Time
Reset to Empty Flag Low
Reset to Half-Full and Full Flag High
Retransmit Low to Flags Valid
Read Low to Empty Flag Low
Read High to Full Flag High
Read Pulse Width after
EF
High
Write High to Empty Flag High
Write Low to Full Flag Low
Write Low to Half-Full Flag Low
Read High to Half-Full Flag High
Write Pulse Width after
FF
High
Read/Write to
XO
Low
Read/Write to
XO
High
XI
Pulse Width
(3)
XI
Recovery Time
XI
Setup Time
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for the 25ns speed grade is available as a standard device.
All other speed grades are available by special order.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
3.3V
330Ω
D.U.T.
510Ω
30pF*
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
3
3033 drw 03
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D
0
– D
8
)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power up before a write operation can take
place.
Both the Read Enable (R) and Write Enable (W) inputs must be
in the HIGH state during the window shown in Figure 2, (i.e., t
RSS
before the rising edge of
RS
) and should not change until t
RSR
after
the rising edge of
RS.
Half-Full Flag (HF) will be reset to HIGH after
Reset (RS).
WRITE ENABLE (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF)
is not set. Data setup and hold times must be adhered to with respect to the rising
edge of the Write Enable (W). Data is stored in the RAM array sequentially and
independently of any ongoing read operation.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by the rising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read operation, the Full Flag
(FF) will go HIGH after t
RFF
, allowing a valid write to begin. When the FIFO
is full, the internal write pointer is blocked from
W,
so external changes in
W
will
not affect the FIFO when it is full.
READ ENABLE (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided
the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis,
independent of any ongoing write operations. After Read Enable (R) goes
HIGH, the Data Outputs (Q
0
– Q
8
) will return to a high impedance condition until
the next Read operation. When all data has been read from the FIFO, the Empty
Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the Empty Flag (EF) will go HIGH
after t
WEF
and a valid Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from
R
so external changes in
R
will not affect the FIFO
when it is empty.
FIRST LOAD/RETRANSMIT (FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first loaded (see Operating Modes). In the Single
Device Mode, this pin acts as the retransmit input. The Single Device Mode is
initiated by grounding the Expansion In (XI).
These FIFOs can be made to retransmit data when the Retransmit Enable
control (RT) input is pulsed LOW. A retransmit operation will set the internal read
pointer to the first location and will not affect the write pointer. Read Enable (R)
and Write Enable (W) must be in the HIGH state during retransmit. This feature
is useful when less than 512/1,024/2,048/4,096/8,192/16,384 writes are
performed between resets. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on
the relative locations of the read and write pointers.
EXPANSION IN (XI)
This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate
an operation in the single device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
OUTPUTS:
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
write pointer is one location less than the read pointer, indicating that the device
is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will
go LOW after 512/1,024/2,048/4,096/8,192/16,384 writes to the IDT72V01/
72V02/72V03/72V04/72V05/72V06.
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (XO/HF)
This is a dual-purpose output. In the single device mode, when Expansion
In (XI) is grounded, this output acts as an indication of a half-full memory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Out (XO) of the previous device. This output acts as a signal to the next device
in the Daisy Chain by providing a pulse to the next device when the previous
device reaches the last location of memory.
DATA OUTPUTS (Q
0
– Q
8
)
Data outputs for 9-bit wide data. This data is in a high impedance condition
whenever Read (R) is in a HIGH state.
4
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
RSC
RS
W
t
RSS
R
t
EFL
EF
t
HFH,
t
FFH
HF, FF
NOTES:
1.
EF, FF, HF
may change status during Reset, but flags will be valid at t
RSC
.
2.
W
and
R
= V
IH
around the rising edge of
RS.
3033 drw 04
t
RS
t
RSS
t
RSR
Figure 2. Reset
t
RC
t
A
R
t
RLZ
Q
0
-Q
8
t
WPW
W
t
DS
D
0
-D
8
t
RR
t
RPW
t
A
t
DV
t
RHZ
DATA
OUT
VALID
DATA
OUT
VALID
t
WC
t
WR
t
DH
DATA
IN
VALID
3033 drw 05
DATA
IN
VALID
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
R
W
t
WFF
FF
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
t
RFF
3033 drw 06
Figure 4. Full Flag From Last Write to First Read
5
微控制器 MCU
