3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
4,096 x 4,096
.EATURES:
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IDT72V70840
32 serial input and output streams
4,096 x 4,096 channel non-blocking switching at 8.192 Mb/s
Accepts data streams at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applica-
tions
Automatic identification of ST-BUS
®
and GCI serial streams
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel processor mode to allow microprocessor writes to
TX streams
Direct microprocessor access to all internal memories
Memory block programming for quick set-up
IEEE-1149.1 (JTAG) Test Port
Internal Loopback for testing
Available in 144-pin Thin Quad Flatpack (TQFP) and
144-pin Ball Grid Array (BGA) packages
Operating Temperature Range -40°C to +85°C
°
°
3.3V I/O with 5V tolerant inputs and TTL compatible outputs
DESCRIPTION:
The IDT72V70840 has a non-blocking switch capacity of 1,024 x 1,024
channels at 2.048 Mb/s, 2,048 x 2,048 channels at 4.096 Mb/s, and 4,096 x
4,096 channels at 8.192 Mb/s. With 32 inputs and 32 outputs, programmable
per stream control, and a variety of operating modes the IDT72V70840 is
designed for the TDM time slot interchange function in either voice or data
applications.
Some of the main features of the IDT72V70840 are low power 3.3 Volt
operation, automatic ST-BUS
®
/GCI sensing, memory block programming,
simple microprocessor interface, one cycle direct internal memory accesses,
.UNCTIONAL BLOCK DIAGRAM
Vcc GND
RESET
TMS
TDI
TDO
TCK
TRST
ODE
Test Port
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
Loopback
Output
MUX
Data Memory
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Internal
Registers
Connection
Memory
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
TX16
TX17
TX18
TX19
TX20
TX21
TX22
TX23
TX24
TX25
TX26
TX27
TX28
TX29
TX30
TX31
Timing Unit
Microprocessor Interface
5715 drw01
CLK
F0i
FE/ WFPS
HCLK
DS
CS
R/W
A0-A13
DTA
D0-D15
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
is a trademark of Mitel Corp.
JANUARY 2002
DSC-5715/3
1
2001
Integrated Device Technology, Inc. All rights reserved.
Product specifications subject to change without notice.
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIAL TEMPERATURE RANGE
PIN CON.IGURATIONS
A1 BALL PAD CORNER
A
RX0
RX1
RX3
RX6
TX1
TX4
TX7
RX10
RX12
RX15
TX10
TX11
B
CLK
ODE
RX2
RX5
TX0
TX3
TX6
RX9
RX13
RX14
TX9
TX12
C
F0i
FE/HCLK
RESET
RX4
RX7
TX2
TX5
RX8
RX11
TX8
TX13
TX14
D
TMS
WFPS
TDI
GND
VCC
VCC
VCC
VCC
VCC
TX15
RX16
RX17
E
TD0
TCK
TRST
VCC
GND
GND
GND
GND
VCC
RX19
RX20
RX21
F
G
DS
CS
R/W
VCC
GND
GND
GND
GND
VCC
RX22
RX23
RX18
A0
A1
A2
VCC
GND
GND
GND
GND
VCC
TX16
TX17
TX18
H
J
A3
A4
A5
VCC
GND
GND
GND
GND
VCC
TX19
TX20
TX21
A6
A7
A8
D15
VCC
VCC
VCC
VCC
GND
TX22
RX24
TX23
K
L
M
A9
A10
DTA
D9
D6
D3
D0
TX29
TX26
RX27
RX25
RX26
A11
A12
D12
D11
D7
D4
D1
TX30
TX27
TX24
RX28
RX29
A13
D14
D13
D10
D8
D5
D2
TX31
TX28
TX25
RX31
RX30
1
2
3
4
5
6
7
8
9
10
11
12
5715 drw 02
NOTE:
1. All I/O pins are 5V tolerant except for TMS, TDI and
TRST.
BGA: 1mm pitch, 13mm x 13mm (BC144-1, order code: BC)
TOP VIEW
2
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIAL TEMPERATURE RANGE
PIN CON.IGURATIONS (CONTINUED)
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
GND
TX16
TX17
TX12
TX13
GND
TX18
TX19
GND
ODE
RESET
GND
CLK
FOi
FE/HCLK
WFPS
V
CC
TMS
TDI
TDO
TCK
TRST
GND
DS
CS
R/W
V
CC
A0
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
A12
A13
GND
DTA
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TX11
TX10
GND
TX9
TX8
V
CC
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
GND
TX7
TX6
V
CC
TX5
TX4
GND
TX3
TX2
V
CC
TX1
TX0
GND
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
V
CC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TX22
TX23
GND
TX14
TX15
TX20
TX21
V
CC
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
V
CC
V
CC
V
CC
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
V
CC
TX24
TX25
GND
TX26
TX27
V
CC
TX28
TX29
GND
TX30
TX31
V
CC
D0
D1
GND
D2
D3
V
CC
D4
D5
GND
D6
D7
V
CC
D08
D09
GND
D10
D11
V
CC
D12
D13
GND
D14
D15
5715 drw 03
NOTE:
1. All I/O pins are 5V tolerant except for TMS, TDI and
TRST.
TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)
TOP VIEW
3
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
GND
V
CC
TX0-31
RX0-31
F0i
NAME
Ground.
V
CC
TX Output 0 to 31
(Three-state Outputs)
RX Input 0 to 31
Frame Pulse
I/O
DESCRIPTION
Ground Rail.
+3.3 Volt Power Supply.
Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS
®
and GCI specifications.
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the
HCLK (4.096 MHZ clock) is required for frame alignment in the wide frame pulse (WFP) mode.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-31). This input accepts a 4.096 MHz clock
when data streams @ 2.048 Mb/s, a 8.192 MHz clock when data streams @ 4.096 Mb/s, a 16.384 MHz
clock when data streams @ 8.192 Mb/s.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
Provides the clock to the JTAG test logic.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
to ensure that the IDT72V70840 is in the normal functional mode.
This input (active LOW) puts the IDT72V70840 in its reset state that clears the device internal counters,
registers and brings TX0-31 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the
RESET
pin must be held LOW for a minimum of 100ns to reset the device.
When 1, enables the wide frame pulse (SFP) Frame Alignment interface. When 0, the device operates in
ST-BUS
®
/GCI mode.
This active LOW input works in conjunction with
CS
to enable the read and write operations.
This input controls the direction of the data bus lines during a microprocessor access.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70840.
These pins allow direct access to Connection Memory, Data Memory and internal control registers.
These pins are the data bits of the microprocessor port.
This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of
the CR register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per
channel control bit in the connection memory.
O
I
I
I
I
FE/HCLK Frame Evaluation/
HCLK Clock
CLK
Clock
TMS
TDI
TDO
TCK
TRST
Test Mode Select
Test Serial Data In
Test Serial Data Out
Test Clock
Test Reset
I
I
O
I
I
RESET
Device Reset
(Schmitt Trigger Input)
I
WFPS
DS
R/W
CS
A0-13
D0-15
DTA
Wide Frame Pulse Select
Data Strobe
Read/Write
Chip Select
Address Bus 0 to 13
Data Bus 0-15
Data Transfer
Acknowledgment
Output Drive Enable
I
I
I
I
I
I/O
O
ODE
I
4
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIAL TEMPERATURE RANGE
DECRIPTION (CONTINUED)
JTAG Test Access Port (TAP) and per stream programmable input offset delay,
variable or constant throughput modes, internal loopback, output enable, and
Processor Mode.
The IDT72V70840 is capable of switching up to 4,096 x 4,096 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per channel basis.
The 32 serial input streams (RX) of the IDT72V70840 can be run up to
8.192 Mb/s allowing 128 channels per 125µs frame. The data rates on the output
streams (TX) are identical to those on the input stream.
With two main operating modes, Processor Mode and Connection Mode,
the IDT72V70840 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor (Connection Memory). As
control and status information is critical in data transmission, the Processor Mode
is especially useful when there are multiple devices sharing the input and output
streams.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V70840
has a frame evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +4.5 clock cycles.
The IDT72V70840 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS
®
/GCI sensing to shorten setup time, aid in
debugging and ease use of the device without sacrificing capabilities.
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate, e.g. for a
serial data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz.
The input and output stream data rates will always be identical. See control
register bits DR1-0 description (Table 5) for data and clock rate selections.
The IDT72V70840 provides two different interface timing modes, ST-BUS
®
or GCI. The IDT72V70840 automatically detects the presence of an input frame
pulse and identifies it as either ST-BUS
®
or GCI. In ST-BUS
®
format, every
second falling edge of the master clock marks a bit boundary and the data is
clocked in on the rising edge of CLK, three quarters of the way into the bit cell.
In GCI format, every second rising edge of the master clock marks the bit
boundary and data is clocked in on the falling edge of CLK at three quarters
of the way into the bit cell.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment (i.e.
F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
data is often delayed this feature is useful in compensating for the skew between
clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 8). The maximum allowable skew is
+4 master clock (CLK) periods forward with a resolution of 1/2 clock period. The
output frame offset cannot be offset or adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70840 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the Control Register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle is started.
In ST-BUS
®
mode, the falling edge of the frame measurement signal (FE)
is evaluated against the falling edge of the ST-BUS
®
frame pulse. In GCI mode,
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 7 and Figure 1 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
The IDT72V70840 provides users with the capability of initializing the entire
connection memory block in two frames. To set bits 12 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 8 of the Control
Register.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the Control Register is set to high, the block programming
data will be loaded into the bits 12 to 15 of every connection memory location.
The other connection memory bits (bit 0 to bit 11) are loaded with zeros. When
the memory block programming is complete, the device resets the BPE bit to
zero.
.UNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially
address the input channels in Data Memory.
Data output on the TX streams may come from either the Serial Input Streams
(Data Memory) or from the microprocessor (Connection Memory). In the case
that RX input data is to be output, the addresses in connection memory are used
to specify a stream and channel of the input. The connection memory is setup
in such a way that each location corresponds to an output channel for each
particular stream. In that way, more than one channel can output the same data.
In Processor Mode, the microprocessor writes data to the connection
memory locations corresponding to the stream and channel that is to be output.
The lower half (8 least significant bits) of the connection memory is output every
frame until the microprocessor changes the data or mode of the channel. By
using this Processor Mode capability, the microprocessor can access input and
output time-slots on a per channel basis.
The four most significant bits of the connection memory are used to control
per channel functions of the out put streams. Specifically, there are bits for
Processor or Connection mode, Constant or Variable delay, enables or
disables of output drivers, and controls for the Loopback function.
If the per channel OE is set to zero, only that particular channel (8-bits) will
be in the high-impedance state. If however, the ODE input pin is low or the Output
Standby Bit (OSB) in the Control Register is low, all of the outputs will be in a
high-impedance state even if a particular channel in connection memory has
enabled the output for that channel. In other words, the ODE pin and OSB control
bit are master output enables for the device (Table 3).
5
