3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
DUAL 512 x 9, DUAL 1,024 x 9
DUAL 2,048 x 9, DUAL 4,096 X 9
DUAL 8,192 X 9
IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
FEATURES:
•
•
•
•
•
•
DESCRIPTION:
The IDT72V81/72V82/72V83/72V84/72V85 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional and
compatible to two IDT72V01/72V02/72V03/72V04/72V05 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity
bits at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when
RT
is pulsed low to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology.
They are designed for those applications requiring asynchronous and simul-
taneous read/writes in multiprocessing and rate buffer applications.
•
•
•
•
•
•
•
•
•
•
The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs
The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs
The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs
The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs
The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs
Low power consumption
— Active: 330 mW (max.)
— Power-down: 18 mW (max.)
Ultra high speed—15 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bidirectional, width expansion, depth expansion, bus-
matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS™ technology
Space-saving TSSOP package
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(DA
0
-DA
8
)
WA
WRITE
CONTROL
WRITE
POINTER
THREE-
STATE
BUFFERS
RSA
WB
WRITE
CONTROL
WRITE
POINTER
DATA INPUTS
(DB
0
-DB
8
)
RSB
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
THREE-
STATE
BUFFERS
RA
READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
RESET
LOGIC
READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
RESET
LOGIC
XIA
XOA/HFA
FFA
EFA
DATA
OUTPUTS
(QA
0
-QA
8
)
FLA/RTA
RB
XIB
XOB/HFB
FFB
EFB
DATA
OUTPUTS
(QB
0
-QB
8
)
FLB/RTB
3966 drw 01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The AsyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERICAL TEMPERATURE RANGE
JULY 2006
DSC-3966/2
1
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
FFA
QA
0
QA
1
QA
2
QA
3
QA
8
GND
RA
QA
4
QA
5
QA
6
QA
7
XOA/HFA
EFA
FFB
QB
0
QB
1
QB
2
QB
3
QB
8
GND
RB
QB
4
QB
5
QB
6
QB
7
XOB/HFB
EFB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
XIA
DA
0
DA
1
DA
2
DA
3
DA
8
WA
V
CC
DA
4
DA
5
DA
6
DA
7
FLA/RTA
RSA
XIB
DB
0
DB
1
DB
2
DB
3
DB
8
WB
V
CC
DB
4
DB
5
DB
6
DB
7
FLB/RTB
RSB
3966 drw 02
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Commercial
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
(1)
V
IL
(2)
T
A
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Commercial
Min.
3.0
0
2.0
—
0
Typ.
3.3
0
—
—
—
Max.
3.6
0
V
CC
+0.5
0.8
70
Unit
V
V
V
V
°C
NOTES:
1. For
RT/RS/XI
input, V
IH
= 2.6V (commercial).
2. 1.5V undershoots are allowed for 10ns once per cycle.
TSSOP (SO56-2, order code: PA)
TOP VIEW
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Condition
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
DC ELECTRICAL
CHARACTERISTICS
(1)
(Commercial: V
CC
= 3.3V±0.3V, T
A
= 0°C to +70°C)
IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
Commercial
t
A
= 15, 20 ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3,4)
I
CC2(3,5)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage
I
OH
= –2mA
Output Logic “0” Voltage
I
OL
= 8mA
Active Power Supply Current (both FIFOs)
Standby Current (R=W=RS=FL/RT=V
IH
)
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
100
5
Unit
µA
µA
V
V
mA
mA
NOTE:
1. Characterized values, not currently tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
3.3V
330Ω
TO
OUTPUT
PIN
510Ω
30pF*
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
R
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs open (I
OUT
= 0).
4. Tested at f = 20 MHz.
5. All Inputs = V
CC
- 0.2V or GND + 0.2V.
3966 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes scope and jib capacitances.
2
JULY 17, 2006
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: V
CC
= 3.3V±0.3V, T
A
= 0°C to +70°C)
Commercial
IDT72V81L15
IDT72V82L15
IDT72V83L15
IDT72V84L15
IDT72V85L15
Symbol
t
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RSR
t
RTC
t
RT
t
RTS
t
RTR
t
EFL
t
HFH,FFH
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
Parameter
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
(2)
Read Pulse Low to Data Bus at Low Z
(3)
Write Pulse High to Data Bus at Low Z
(3, 4)
Data Valid from Read Pulse High
Read Pulse High to Data Bus at High Z
(3)
Write Cycle Time
Write Pulse Width
(2)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(2)
Reset Set-up Time
(3)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(2)
Retransmit Set-up Time
(3)
Retransmit Recovery Time
Reset to Empty Flag Low
Reset to Half-Full and Full Flag High
Retransmit Low to Flags Valid
Read Low to Empty Flag Low
Read High to Full Flag High
Read Pulse Width after
EF
High
Write High to Empty Flag High
Write Low to Full Flag Low
Write Low to Half-Full Flag Low
Read High to Half-Full Flag High
Write Pulse Width after
FF
High
Read/Write to
XO
Low
Read/Write to
XO
High
XI
Pulse Width
(2)
XI
Recovery Time
XI
Set-up Time
Min.
—
25
—
10
15
3
5
5
—
25
15
10
11
0
25
15
15
10
25
15
15
10
—
—
—
—
—
15
—
—
—
—
15
—
—
15
10
10
Max.
40
—
15
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
25
25
25
15
15
—
15
15
25
25
—
15
15
—
—
—
IDT72V81L20
IDT72V82L20
IDT72V83L20
IDT72V84L20
IDT72V85L20
Min.
—
30
—
10
20
3
5
5
—
30
20
10
12
0
30
20
20
10
30
20
20
10
—
—
—
—
—
20
—
—
—
—
20
—
—
20
10
10
Max.
33.3
—
20
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
20
20
—
20
20
30
30
—
20
20
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
3
JULY 17, 2006
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D
0
– D
8
)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (
RS
)
Reset is accomplished whenever the Reset (RS) input is taken to a low state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power up before a write operation can take place.
Both
the Read Enable (
R
) and Write Enable (
W
) inputs must be in the high
state during the window shown in Figure 2, (i.e., t
RSS
before the rising
edge of
RS
) and should not change until t
RSR
after the rising edge of
RS.
Half-Full Flag (
HF
) will be reset to high after Reset (
RS
).
WRITE ENABLE (
W
)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF)
is not set. Data set-up and hold times must be adhered to with respect to the rising
edge of the Write Enable (W). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set to low and will remain set until the
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by the rising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write
operations. Upon the completion of a valid read operation, the Full Flag (FF)
will go high after t
RFF
, allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from
W,
so external changes in
W
will not affect
the FIFO when it is full.
READ ENABLE (
R
)
A read cycle is initiated on the falling edge of the Read Enable (R) provided
the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis,
independent of any ongoing write operations. After Read Enable (R) goes high,
the Data Outputs (Q
0
– Q
8
) will return to a high impedance condition until the
next Read operation. When all data has been read from the FIFO, the Empty
Flag (EF) will go low, allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the Empty Flag (EF) will go high
after t
WEF
and a valid Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from
R
so external changes in
R
will not affect the FIFO
when it is empty.
FIRST LOAD/RETRANSMIT (
FL/RT
)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first loaded (see Operating Modes). In the
Single Device Mode, this pin acts as the retransmit input. The Single Device
Mode is initiated by grounding the Expansion In (XI).
The IDT72V81/72V82/72V83/72V84/72V85 can be made to retransmit
data when the Retransmit Enable control (RT) input is pulsed low. A retransmit
operation will set the internal read pointer to the first location and will not affect
the write pointer. Read Enable (R) and Write Enable (W) must be in the high
state during retransmit for the IDT72V81/72V82/72V83/72V84/72V85 respec-
tively. This feature is useful when less than 512/1,024/2,048/4,096/8,192 writes
are performed between resets. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on
the relative locations of the read and write pointers.
EXPANSION IN (
XI
)
This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate
an operation in the single device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
FULL FLAG (
FF
)
The Full Flag (FF) will go low, inhibiting further write operation, when the write
pointer is one location less than the read pointer, indicating that the device is full.
If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go low
after 512 writes for the IDT72V81, 1,024 writes for the IDT72V82, 2,048 writes
for the IDT72V83, 4,096 writes for the IDT72V84 and 8,192 writes for the
IDT72V85.
EMPTY FLAG (
EF
)
The Empty Flag (EF) will go low, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG (
XO/HF
)
This is a dual-purpose output. In the single device mode, when Expan-
sion In (XI) is grounded, this output acts as an indication of a half-full memory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set low and will remain set until the
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Out (XO) of the previous device in the Daisy Chain by providing a pulse to the
next device when the previous device reaches the last location of memory.
DATA OUTPUTS ( Q
0
– Q
8
)
Data outputs for 9-bit wide data. This data is in a high impedance
condition whenever Read (R) is in a high state.
OUTPUTS:
4
JULY 17, 2006
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
t
RSC
RS
W
t
RSS
R
t
EFL
EF
t
HFH,
t
FFH
HF, FF
NOTES:
1.
EF, FF, HF
may change status during Reset, but flags will be valid at t
RSC
.
2.
W
and
R
= V
IH
around the rising edge of
RS.
Figure 2. Reset
3966 drw 04
t
RS
t
RSS
t
RSR
t
RC
t
A
R
t
RLZ
Q
0
-Q
8
t
WPW
W
t
DS
D
0
-D
8
t
RPW
t
RR
t
DV
t
A
t
RHZ
DATA OUT VALID
DATA OUT VALID
t
WC
t
WR
t
DH
DATA IN VALID
3966 drw 05
DATA IN VALID
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
R
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
W
t
WFF
FF
Figure 4. Full Flag From Last Write to First Read
t
RFF
3966 drw 06
5
JULY 17, 2006
