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IDT74FCT162344ETPA

Bus Driver, FCT Series, 4-Func, 2-Bit, True Output, CMOS, PDSO56, TSSOP-56

器件类别:逻辑    逻辑   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
IDT (Integrated Device Technology)
零件包装代码
TSSOP
包装说明
TSSOP, TSSOP56,.3,20
针数
56
Reach Compliance Code
not_compliant
系列
FCT
JESD-30 代码
R-PDSO-G56
JESD-609代码
e0
长度
14 mm
负载电容(CL)
50 pF
逻辑集成电路类型
BUS DRIVER
湿度敏感等级
1
位数
2
功能数量
4
端口数量
2
端子数量
56
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE WITH SERIES RESISTOR
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP56,.3,20
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
5 V
传播延迟(tpd)
3.8 ns
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn85Pb15)
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
6.1 mm
文档预览
FAST CMOS ADDRESS/
CLOCK DRIVER
Integrated Device Technology, Inc.
IDT54/74FCT162344AT/CT/ET
FEATURES:
0.5 MICRON CMOS Technology
Ideal for address line driving and clock distribution
8 banks with 1:4 fanout and 3-state
Typical t
SK
(o) (Output Skew) < 500ps
Balanced Output Drivers:
±24mA
(commercial),
±16mA
(military)
Reduced system switching noise
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40°C to +85°C
V
CC
= 5V
±10%
Low input and output leakage
1µA (max.)
DESCRIPTION:
The FCT162344AT/CT/ET is a 1:4 address line driver built
using advanced dual metal CMOS technology. This high-
speed, low power device provides the ability to fanout to
memory arrays. Eight banks, each with a fanout of 4, and 3-
state control provide efficient address distribution. One or
more banks may be used for clock distribution.
The FCT162344AT/CT/ET has balanced output drive with
current limiting resistors. This offers low ground bounce,
minimal undershoot and controlled output fall times reducing
the need for external series terminating resistors.
A large number of power and ground pins and TTL output
swings also ensure reduced noise levels. All inputs are
designed with hysteresis for improved noise margins.
FUNCTIONAL BLOCK DIAGRAM
OE
1
B
11
A
1
B
14
B
21
A
2
B
24
A
6
A
5
OE
3
B
51
B
54
B
61
B
64
OE
2
B
31
A
3
B
34
B
41
A
4
B
44
A
8
A
7
OE
4
B
71
B
74
B
81
B
84
3069 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-3069/3
5.6
1
IDT54/74FCT162344AT/CT/ET
FAST CMOS ADDRESS LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE1
B
11
B
12
GND
B
13
B
14
V
CC
A
1
B
21
B
22
GND
B
23
B
24
A
2
A
3
B
31
B
32
GND
B
33
B
34
A
4
V
CC
B
41
B
42
GND
B
43
B
44
OE2
1
2
3
4
5
6
7
8
9
10
11
12
13
56
55
54
53
52
51
50
49
48
47
46
45
44
OE4
B
81
B
82
GND
B
83
B
84
V
CC
A
8
B
71
B
72
GND
B
73
B
74
A
7
A
6
B
61
B
62
GND
B
63
B
64
A
5
V
CC
B
51
B
52
GND
B
53
B
54
OE3
OE1
B
11
B
12
GND
B
13
B
14
V
CC
A
1
B
21
B
22
GND
B
23
B
24
A
2
A
3
B
31
B
32
GND
B
33
B
34
A
4
V
CC
B
41
B
42
GND
B
43
B
44
OE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CERPACK
TOP VIEW
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE4
B
81
B
82
GND
B
83
B
84
V
CC
A
8
B
71
B
72
GND
B
73
B
74
A
7
A
6
B
61
B
62
GND
B
63
B
64
A
5
V
CC
B
51
B
52
GND
B
53
B
54
OE3
14 SO56-1 43
SO56-2
15 SO56-3 42
16
17
18
19
20
21
22
23
24
25
26
27
28
41
40
39
38
37
36
35
34
33
32
31
30
29
SSOP/
TSSOP/TVSOP
TOP VIEW
3069 drw 02
3069 drw 03
5.6
2
IDT54/74FCT162344AT/CT/ET
FAST CMOS ADDRESS LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
OE
x
Ax
Bxx
Description
3–State Output Enable Inputs (Active LOW)
Inputs
3-State Outputs
3069 tbl 01
FUNCTION TABLE
(1)
OE
x
L
L
H
Inputs
Ax
L
H
X
Outputs
Bxx
L
H
Z
3069 tbl 02
ABSOLUTE MAXIMUM RATINGS
(1)
Unit
V
V
°C
mA
Symbol
Description
Max.
(2)
Terminal Voltage with Respect to –0.5 to +7.0
V
TERM
GND
V
TERM(3)
Terminal Voltage with Respect to
–0.5 to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max. Unit
6.0
pF
8.0
pF
3069 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
NOTE:
1. This parameter is measured at characterization but not tested.
3069 lnk 04
5.6
3
IDT54/74FCT162344AT/CT/ET
FAST CMOS ADDRESS LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40°C to +85°C, V
CC
= 5.0V
±
10%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= GND
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
Min.
2.0
–80
Typ.
(2)
0.7
140
Max.
Unit
V
V
µA
0.8
±1
±1
±1
±1
±1
±1
1.2
225
µA
V
mA
mV
µA
100
5
V
CC
= Max., V
IN
= GND or V
CC
500
3069 lnk 05
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –16mA MIL.
I
OH
= –24mA COM'L.
I
OL
= 16mA MIL.
I
OL
= 24mA COM'L.
Min.
60
–60
2.4
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
0.55
Unit
mA
mA
V
V
3069 lnk 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
±
5µA at T
A
= –55°C.
5.6
4
IDT54/74FCT162344AT/CT/ET
FAST CMOS ADDRESS LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
x = GND
One Input Bit Toggling
Four Output Bits Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE
x = GND
One Input Bit Toggling
Four Output Bits Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE
x = GND
Eight Input Bits Toggling
Thirty Two Output Bits Toggling
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
Typ.
(2)
0.5
170
Max.
1.5
220
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
1.7
2.7
mA
2.0
3.5
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
3.4
4.9
(5)
5.4
10.9
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
3069 tbl 07
5.6
5
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