Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
Selects between
÷
1 and
÷
2 frequency options. (Refer to functional block diagram).
Feedback input to phase detector.
Input for external loop filter connection.
Clock output.
Inverted clock output.
Clock output (2 x Q frequency).
Clock output (Q frequency
÷
2).
Indicates phase lock has been achieved (HIGH when locked).
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
3072 tbl 01
Description
9.7
2
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
V
TERM(2)
Terminal Voltage
with Respect to
GND
V
TERM(3)
Terminal Voltage
with Respect to
GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
I
OUT
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max.
6.0
8.0
Unit
pF
pF
3072 lnk 03
–0.5 to V
CC
+0.5
0 to +70
–55 to +125
–55 to +125
–60 to +120
–0.5 to V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
–60 to +120
V
°C
°C
°C
mA
NOTE:
1. This parameter is measured at characterization but not tested.
3072 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals.
3. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to 70°C, V
CC
= 5.0V
±
5%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
V
H
V
OH
Clamp Diode Voltage
Input Hysteresis
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= GND
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Min., I
IN
= –18mA
—
I
OH
= –3mA
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OH
= –24mA MIL.
I
OH
= –32mA COM'L.
(3)
V
CC
= Min.
I
OL
= 48mA MIL.
V
IN
= V
IH
or V
IL
I
OL
= 64mA COM'L.
V
CC
= Max., V
IN
= GND or V
CC
(Test mode)
Min.
2.0
—
—
—
—
—
—
—
2.5
2.4
2.0
—
—
Typ.
(2)
—
—
—
—
—
—
–0.7
100
3.5
3.5
3.0
0.2
2.0
Max.
—
0.8
±1
±1
±1
±1
–1.2
—
—
—
—
0.55
4.0
Unit
V
V
µA
µA
µA
µA
V
mV
V
V
V
V
mA
V
OL
I
CCL
I
CCH
I
CCZ
Output LOW Voltage
Quiescent Power Supply Current
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Duration of the condition can not exceed one second.
3072 tbl 04
9.7
3
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
C
PD
I
C
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Power Dissipation Capacitance
Total Power Supply Current
(5,6)
Test Conditions
(1)
V
CC
= Max.
V
IN
= V
CC
–2.1V
(3)
V
CC
= Max.
All Outputs Open
50% Duty Cycle
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q/2
SYNC frequency = 20MHz. Q/2 loaded with 50pF
All other outputs open
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q/2
SYNC frequency = 20MHz. Q/2 loaded with 50Ω
Thevenin termination. All other outputs open
3072 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency
I
LOAD
= Dynamic Current due to load.
Min.
—
Typ.
(2)
0.5
0.25
15
25
Max.
1.5
0.4
40
40
Unit
mA
mA/
MHz
pF
mA
V
IN
= V
CC
V
IN
= GND
—
—
—
—
42
60
mA
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
T
RISE/FALL
Rise/Fall Times,
SYNC inputs
(0.8V to 2.0V)
Frequency Input Frequency,
SYNC Inputs
Duty Cycle Input Duty Cycle,
SYNC Inputs
Min.
—
Max.
3.0
Unit
ns
10
(1)
25%
2Q fmax
75%
MHz
—
3053 tbl 06
OUTPUT FREQUENCY SPECIFICATIONS
Max.
(2)
Symbol
f2Q
fQ
fQ/2
Parameter
Operating frequency 2Q Output
Operating frequency Q0-Q4, Q5 Outputs
Operating frequency Q/2 Output
Min.
40
20
10
55
55
27.5
13.75
70
70
35
17.5
100
100
50
25
133
133
66.7
33.3
Unit
MHz
MHz
MHz
3072 tbl 07
NOTES:
1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
9.7
4
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
RISE/FALL
All outputs
t
PULSE WIDTH (3)
All outputs
(3)
Parameter
Rise/Fall Time
(between 0.8V and 2.0V)
Output Pulse Width
Q0-Q4, Q5, Q/2, 2Q @ 1.5V
Load = 50Ω to
V
CC
/2, C
L
= 20pF
0.1µF from LF to
Analog GND
(9)
Load = 50Ω to
V
CC
/2, C
L
= 20pF
Condition
(1)
Load = 50Ω to
V
CC
/2, C
L
= 20pF
Min.
0.2
(2)
0.5t
CYCLE
– 0.5
(5)
–0.5
Max.
1.2
0.5t
CYCLE
+ 0.5
(5)
+0.5
Unit
ns
ns
ns
SYNC input to FEEDBACK delay
t
PD
(3)
(measured at SYNC0 or 1 and FEEDBACK
SYNC-FEEDBACK
input pins)
t
SKEW
r
(rising)
(3,4)
t
SKEW
f
(falling)
(3,4)
t
SKEW
all
t
LOCK (6)
(3,4)
Output to Output Skew
between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
Time required to acquire
Phase-Lock from time
SYNC input signal is received
Output Enable Time
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
Output Disable Time
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
—
350
ps
—
—
1
(2)
350
500
10
ps
ps
ms
t
PZH
t
PZL
t
PHZ
t
PLZ
3
(2)
3
(2)
14
14
ns
ns
3072 tbl 08
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions, and at a fixed temperature and voltage.
5. t
CYCLE
= 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With V
CC
fully powered-on and an output properly connected to the FEEDBACK pin. t
LOCK
Max. is with C1 = 0.1µF, t
LOCK
Min. is with C1 = 0.01µF.
(Where C1 is loop filter capacitor shown in Figure 1).
