IDT74LVC86A
3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS
QUADRUPLE 2-INPUT
EXCLUSIVE-OR GATE
WITH 5 VOLT TOLERANT I/O
FEATURES:
–
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.65mm pitch SSOP and
0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVC86A
DESCRIPTION
This quadruple 2-input exclusive-OR gate is built using advanced dual
metal CMOS technology. The LVC86A performs the Boolean function Y =
A B or Y =
AB
+
AB
in positive logic. A common application is as a true/
complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other
input is reproduced inverted at the output.
The LVC86A has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
Drive Features for LVC86A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
A
Y
B
PIN CONFIGURATION
1
A
1
B
1
Y
2
A
2
B
2
Y
1
2
3
4
5
6
7
SO14-1
SO14-2
SO14-3
14
13
12
11
10
9
8
V
CC
4
B
4
A
4
Y
3
B
3
A
3
Y
GND
FUNCTION TABLE
(each gate)
(1)
Inputs
xA
L
L
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
xB
L
H
L
H
Outputs
xY
L
H
H
L
SOIC/ SSOP/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xA, xB
xY
Description
Data Inputs
Data Outputs
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4725/-
IDT74LVC86A
3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
LVC QUAD Link
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Unit
V
°C
mA
mA
mA
C
I/O
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
LVC QUAD Link
Max.
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= – 40°c to +85°c
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
10
µA
V
mV
µA
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
µA
µA
V
Unit
V
Quiescent Power Supply
Current Variation
One input at V
CC
– 0.6V
other inputs at V
CC
or GND
—
—
500
µA
LVC QUAD Link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2
IDT74LVC86A
3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
LVC QUAD Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
OPERATING CHARACTERISTICS, TA = 25°C
V
CC
= 2.5V±0.2V
Symbol
Parameter
C
PD
Power Dissipation Capacitance Per Gate
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
—
V
CC
= 3.3V±0.3V
Typical
8.5
Unit
pF
SWITCHING CHARACTERISTICS
Symbol
Parameter
t
PLH
Propagation Delay
xA to xY
t
PHL
tsk(o) Output Skew
(2)
Min
—
—
(1)
V
CC
= 2.7V
Min
—
—
Max
5.6
—
V
CC
= 3.3V±0.3V
Min
1
—
Max
4.6
1
Unit
ns
ns
V
CC
= 2.5V±0.2V
Max
—
—
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
3
IDT74LVC86A
3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 2.5V ±0.2V
2 x Vcc
Vcc
V
CC
/ 2
150
150
30
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
V
CC
(2)
= 3.3V ±0.3V & 2.7V
6
2.7
1.5
300
300
50
Unit
V
V
V
mV
mV
pF
LVC QUAD Link
SA M E PH AS E
IN PU T TR AN S ITIO N
t
PLH
O U TPU T
t
PLH
O PPO SITE P H AS E
IN PU T TR AN S ITIO N
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LV C Q U A D L in k
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
G enerator
(1, 2)
V
LOAD
O pen
GND
ENABLE AND DISABLE TIMES
EN ABLE
C O N TR O L
IN PU T
t
PZL
t
PLZ
V
LOAD/2
V
T
t
PH Z
V
T
0V
D ISAB LE
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
LV C Q U A D L in k
V
IN
D.U.T.
V
OUT
R
T
500
Ω
C
L
L V C Q U A D L in k
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
O U TPU T
SW ITCH
N O R M ALLY
CLO SED
LO W
t
PZH
O U TPU T
SW ITCH
N O R M ALLY
OP EN
H IGH
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
D A TA
IN PU T
TIM IN G
IN PU T
SY N C H RO N O U S
C O N TR O L
LVC QUAD Link
t
SU
t
H
GND
Open
t
REM
OUTPUT SKEW - tsk (x)
V
IH
IN PU T
V
T
0V
V
OH
O U TP U T 1
V
T
V
OL
V
OH
O U TP U T 2
t
PLH2
t
PH L2
V
T
V
OL
t
PLH1
t
PH L1
AS YN C H RO N O U S
C O N TR O L
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
L V C Q U A D L in k
PULSE WIDTH
LO W -H IG H -LO W
PU LSE
t
W
H IGH -LO W -H IG H
PU LSE
V
T
LV C Q U A D L in k
t
SK
(x)
t
SK
(x)
V
T
t
SK
(x)
= t
PL H2
-
t
PLH1
or
t
PH L2
-
t
PHL1
LV C Q U A D L in k
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
4
IDT74LVC86A
3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
Temp. Range
LVC
XXX
Device Type
XX
Package
DC
PY
PG
86A
Small Outline IC (SO14-1)
Shrink Small Outline Package (SO14-2)
Thin Shrink Small Outline Package (SO14-3)
Quadruple 2-Input Exclusive-OR Gate, ±24mA
74
–40°C to +85°C
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