SwitchStar
TM
ATM Cell Based
8 x 8 1.2Gbps non-blocking
Integrated Switching Memory
Features List
Single chip supports an 8 x 8 port switch at 155Mbps per
port
!
Central Memory Architecture eliminates Head-of-Line
Blocking by sharing the memory array with all ports
!
Low power dissipation
– 330mW (typ.)
!
Data Path Interface (DPI) provides configurable Input and
Output ports; up to 8 receive and 8 transmit ports at
155Mbps
!
Supports data rates up to 1.2Gbps with a 32-bit wide port
configuration; 155Mbps per 4-bit port
!
Can be cascaded for larger switch configurations
!
Fast Input/Output port cycle times
!
Expander and Concentrator function is fully supported by
the Input and Output port configuration options
!
8192 cells (52 to 56 bytes each) of on-chip buffer memory
capacity
!
!
IDT77V400
!
!
!
!
!
!
!
!
Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can
be independently chosen for Input and Output ports
Byte Addition or Byte Subtraction for x4/x8 to x16/x32
conversion capability
Internal header Cyclical Redundancy Check (CRC) and
generation logic on-chip
Header modification, pre-pend, and post-pend operations
available as well as Multicasting and Broadcasting
capability
High-bandwidth control port for queue controller system
block, up to 36 MHz cycle time
Can be used with the companion IDT77V500 Switch
Controller or custom logic for traffic management
Industrial temperature range (-40°C to +85°C) is available
Single +3.3V ± 300mV power supply
Available in an 208-pin Plastic Quad Flat Pack (PQFP) and
256-ball BGA
Block Diagram
External Interface
for Global Setup
and Control
8-bit Processor/
Call Setup
Manager
or IDT77V550
Data
Control
IDT77V500
Switch
Controller
Data
Control
155Mbps
PHY
Port 0
Port 0
155Mbps
PHY
,
IDT77V400
Switching
Memory
155Mbps
PHY
Port 7
Port 7
155Mbps
PHY
3606 drw 01
Figure 1 Typical 8x8 Switch Configuration using the IDT77V400 Switching Memory
SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 26
2001 Integrated Device Technology, Inc.
March 31, 2001
DSC 3606/6
IDT77V400
Description
The IDT77V400 ATM Cell Based Switching Memory provides the
logic and memory necessary to perform high-speed buffering and
switching operations on ATM cell data. A single IDT77V400 provides a
cost effective switching element to implement an 8 x 8 155Mbps switch
with 1.2Gbps total switching bandwidth. The user configurable data
ports provide an aggregate bandwidth of 1.2Gbps for both receive and
transmit functions, and the cell lengths are user programmable to up to
56 bytes.
The memory provides storage for 8192 ATM cells, each of which can
be as large as 56-bytes in length. The main cell memory is implemented
as a Buffer Memory array, and an on-chip cell address counter keeps
track of cell refresh requirements. There are also sixteen double-buff-
ered Serial Access Memories (SAM); eight for receiving and eight for
transmitting the ATM cells.
The input data ports and output data ports are configurable from
eight ports of 4-bits at 155Mbps each up to one 32-bit wide port at
1.2Gbps. The sixteen data ports are asynchronous with respect to each
other, and each port provides an independent data clock and cell
framing signal for start of cell indication. The SAMs are double-buffered
for each input and each output port to allow one cell to be transferred to
or from the internal memory while that data port continues to receive or
transmit a second cell. The cell framing and data clock signals imple-
ment a simple handshaking and synchronization protocol which allows
multiple Switching Memories to be connected to construct larger switch
arrays without requiring additional hardware.
The control interface of the IDT77V400 includes a 6-bit Command
Bus (CMD0-5), a 32-bit Control Data Bus (IOD0-31), a Chip Select pin
(CS), a 4-bit Address field (ADDR0-3), a RESET pin, an Output Enable
pin (OE), a Control Enable pin (CTLEN) and a CRCERR pin. All control
operations are synchronized with respect to the System Clock (SCLK),
with the exception of RESET, CTLEN, and OE, which are fully asynchro-
nous.
The internal configuration register of the IDT77V400 can be
accessed through the Control Data Bus to define the cell length and the
input and output data port configurations. Internal error and status regis-
ters contain status information regarding each SAM and are accessible
via the Control Data Bus (IOD0-31). Input SAM full or Output SAM
empty status for all SAMs may be obtained in one access operation.
Additional information regarding the reception of short or long cells and
Input SAM overflow may also be obtained through the Control Data Bus.
The command set of the Switching Memory provides functions for
storing cells in the shared memory, loading Output SAMs, polling the
status of the data ports, retrieving and storing original or modified
header bytes and pre-pend or post-pend bytes, and refreshing the cell
memory. Header CRC errors are indicated by a LOW CRCERR pin; the
CRC comparison byte may also be accessed via the status register,
which indicates the IPort on which the error was detected. A new CRC
can be generated upon storing a new header in the PHEC command.
Cell headers may be modified upon cell reception at the input ports or
upon cell transmit at the output ports. User defined pre-pend and post-
pend bytes may also be stored, retrieved, and modified through the
Control Data Bus.
The IDT77V400 has a generic control interface which supports a
variety of queuing disciplines. By maintaining the memory control in an
external controller, system level switching performance may be modified
over time as requirements change. In normal operation, the Switching
Memory port status is polled by the control function through the Control
Data Bus. Upon receiving a cell, the control function can retrieve the
header, check the CRC result, and store a new header if needed prior to
moving the cell to the shared memory. Pre-pended or post-pended
bytes may also be added or retrieved during this time. The output ports
are polled at the same time to determine when to send new cells to the
Output SAMs. The cell lengths of the input ports do not need to be the
same as the output port cell lengths, although all input ports and output
ports respectively must be configured to the same cell length.
Please refer to the SwichStar User Manual for additional feature
details and implementation information.
The IDT77V400 is fully 3.3V LVTTL compatible, and is packaged in
an 208-pin Plastic Quad Flatpack (PQFP) and a 256-ball BGA.
2 of 26
March 31, 2001
IDT77V400
SBYTE
Config.
Cntl.
Nibble Counters
Pointer Decode + Control
Config.
OFRM
and OCLK
Control
8
4
4
4
4
8
8
8
OCLK0-7
OFRM0-7
OP0D0-3
OP1D0-3
OP2D0-3
OP3D0-3
OP4D0-3
OP5D0-3
OP6D0-3
OP7D0-3
Output SAM Port 0
4
4
4
Output
Latches
and
Buffers
4
4
4
4
4
Output SAM Port 6
4
4
4
4
Output SAM Port 7
1
4
Cntl.
Output
Header
Output
Edit Buffer
Buffer Memory
Random Access Cell Memory
(8192 ATM Cells)
Addr
Input
1
Edit Buffer
Cntl.
4
Memory
Control
Logic
Refresh
Control
CRC Logic
IP0D0-3
IP1D0-3
IP2D0-3
IP3D0-3
IP4D0-3
IP5D0-3
IP6D0-3
IP7D0-3
4
4
4
4
4
4
4
4
4
4
8
4
4
4
Input SAM Port 0
Edit Buffer
Control
Mode Control
and CRC
Error
Register
IOD0-31
Input
Latches
and
Buffers
4
4
4
Input SAM Port 1
Input SAM Port 7
Port
Status
Status
Register
Config.
Configuration
Register
ICLK0-7
8
IFRM0-7
IFRM
and ICLK
Control
Nibble Counters,
Pointer Decode + Control
Control Interface and
Command Control
Config.
ABYTE
Config.
4
6
32
CTLEN
CS
SCLK
OE
CMD0-5
CRCERR
3606 drw 02
RESET
ADDR0-3
IOD0-31
Figure 2 Functional Block Diagram
INPUT
TRANSFER BUS
Bits 0-71
(from ISAM)
OUTPUT
DRAM BUS
Bits 0-71
OUTPUT
TRANSFER BUS
Bits 0-71
(to OSAM)
To DRAM
INPUT EDIT BUFFER
.
8
OR - P/P
OR - HEADER
8
32
32
XOR
BYTE
byte 1
CLEAR
byte 2
byte 3
[second word]
HEC
72
byte 0
BYTE-PUT-PROTECT
[first word]
32
CRC
GEN
8
MUX
OUTPUT EDIT BUFFER
[first word]
32
MUX
[second word]
32
HEC
8
32
32
8
CRC
GEN
COMPARE
32
CRC error
32
IOD BUS Bits 0 - 31
3606 drw 03
Figure 3 Input and Output Edit Buffer Block Diagram
3 of 26
March 31, 2001
IDT77V400
Package Diagram
All V
CC
/V
CCQ
pins must be connected to power supply. All V
SS
pins must be connected to ground supply. Package body is approximately 28mm x
28mm x 3.4mm.
VCCQ
SBYTE
ABYTE
CRCERR
VCC
VSS
IP6D0
IP6D1
IP6D2
IP6D3
IP4D0
IP4D1
IP4D2
IP4D3
VSS
VCC
IP2D0
IP2D1
IP2D2
IP2D3
IP0D0
IP0D1
IP0D2
IP0D3
VCC
VSS
IFRM7
IFRM6
IFRM5
IFRM4
IFRM3
IFRM2
IFRM1
IFRM0
ICLK7
ICLK6
ICLK5
ICLK4
ICLK3
ICLK2
ICLK1
ICLK0
RESET
VCC
VSS
IP1D0
IP1D1
IP1D2
IP1D3
NC
NC
NC
NC
VCC
VSS
VSS
IOD0
IOD1
IOD2
IOD3
IOD4
IOD5
IOD6
IOD7
IOD8
IOD9
VCC
VCC
IOD10
IOD11
IOD12
IOD13
IOD14
IOD15
IOD16
IOD17
IOD18
IOD19
IOD20
VSS
VSS
IOD21
IOD22
IOD23
IOD24
IOD25
IOD26
IOD27
IOD28
IOD29
IOD30
IOD31
VCC
VCC
VSS
VSS
OP0D3
OP0D2
OP0D1
OP0D0
VCC
VCC
VSS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
IDT77V400DS
DS208-1
1
208-Pin PQFP
Top View
2
NC
NC
VCCQ
VCC
OP2D3
OP2D2
OP2D1
OP2D0
VSS
VSS
OP4D3
OP4D2
OP4D1
OP4D0
VCC
VCC
OP6D3
OP6D2
OP6D1
OP6D0
VSS
OFRM0
OFRM1
OFRM2
OFRM3
OFRM4
OFRM5
OFRM6
OFRM7
VSS
VCC
VCC
VSS
OCLK0
OCLK1
OCLK2
OCLK3
OCLK4
OCLK5
OCLK6
OCLK7
CTLEN
OE
VSS
OP7D3
OP7D2
OP7D1
OP7D0
VCC
VCC
VSS
NC
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
NC
VSS
VCC
IP3D0
IP3D1
IP3D2
IP3D3
IP5D0
IP5D1
IP5D2
IP5D3
IP7D0
IP7D1
IP7D2
IP7D3
VSS
VCC
CS
CMD5
CMD4
CMD3
CMD2
CMD1
CMD0
SCLK
ADDR3
ADDR2
ADDR1
ADDR0
VSS
VCC
VSS
OP1D0
OP1D1
OP1D2
OP1D3
VCC
VCC
OP3D0
OP3D1
OP3D2
OP3D3
VSS
VSS
OP5D0
OP5D1
OP5D2
OP5D3
VCC
VCCQ
NC
NC
3606 drw 04
1
This package code is used to reference the package diagram.
2
This text does not indicate orientation of the actual part marking.
4 of 26
March 31, 2001
IDT77V400
Package Diagram
(1,2,3)
BC256-1 BGA
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
ABYTE
C R C E R R
IP
6D1
B1
B2
B3
IP
6D3
IP
4D2
IP
2D1
B4
B5
B6
IP
0D0
IP
0D3
IFRM
4
IFRM
2
ICLK
7
ICLK
4
ICLK
1
RESET
IP
1D1
IP
3D0
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
IOD
1
SBYTE
IP
6D0
IP
6D2
IP
4D1
IP
2D0
C1
C2
C3
C4
C5
C6
IP
2D3
IP
0D2
IFRM
5
IFRM
1
ICLK
6
ICLK
3
ICLK
0
IP
1D0
C7
C8
C9
C10
C11
C12
C13
C14
IP
1D3
IP
3D1
C15
C16
IOD
2
D1
IOD
3
D2
IOD
0
IP
4D0
IP
4D3
IP
2D2
IP
0D1
IFRM
7
IFRM
6
IFRM
3
IFRM
0
ICLK
5
ICLK
2
IP
1D2
IP
3D2
IP
3D3
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
IOD
6
E1
IOD
4
E2
IOD
5
E3
V
CC
E4
V
CC
E5
V
CC
E6
V
CC
E7
V
CC
E8
V
CC
E9
V
CC
E10
V
CC
E11
V
CC
E12
V
CC
E13
IP
5D2
IP
5D1
IP
5D0
E14
E15
E16
IOD
8
F1
IOD
7
F2
IOD
9
F3
V
CC
F4
V
CC
F5
V
CC
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
CC
F11
V
CC
F12
V
CC
F13
IP
7D1
IP
5D3
IP
7D0
F14
F15
F16
IOD
11
IOD
10
IOD
12
G1
G2
G3
V
CC
G4
V
CC
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
CC
G12
V
CC
G13
CS
G14
IP
7D2
IP
7D3
G15
G16
IOD
14
IOD
13
IOD
15
H1
H2
H3
V
CC
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
CC
H13
CMD
3
CMD
5
CMD
4
H14
H15
H16
IOD
17
IOD
16
IOD
18
J1
J2
J3
V
CC
J4
V
SS
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
CC
J13
CMD
0
CMD
2
CMD
1
J14
J15
J16
IOD
20
IOD
21
IOD
19
K1
K2
K3
V
CC
K4
V
SS
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
CC
K13
SCLK
ADDR
2
ADDR
3
K14
K15
K16
IOD
23
L1
IOD
24
IOD
22
L2
L3
V
CC
L4
V
SS
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
CC
ADDR
0
OP
1D0
ADDR
1
L13
L14
L15
L16
IOD
26
IOD
27
IOD
25
M1
M2
M3
V
CC
M4
V
CC
M5
V
SS
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
CC
M12
V
CC
OP
1D2
OP
1D3
OP
1D1
M13
M14
M15
M16
IOD
29
IOD
30
IOD
28
N1
N2
N3
V
CC
N4
V
CC
N5
V
CC
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
CC
N11
V
CC
N12
V
CC
OP
3D1
OP
3D2
OP
3D0
N13
N14
N15
N16
OP
0D3
OP
0D2
IOD
31
P1
P2
P3
V
CC
P4
V
CC
P5
V
CC
P6
V
CC
P7
V
CC
P8
V
CC
P9
V
CC
P10
V
CC
P11
V
CC
P12
V
CC
OP
5D0
OP
5D1
OP
3D3
P13
P14
P15
P16
OP
0D1
OP
0D0
R1
R2
NC
R3
OP
2D0
OP
4D0
OP
6D1
OFRM
1
OFRM
4
OFRM
5
OCLK
0
OCLK
3
OCLK
6
R4
R5
R6
R7
R8
R9
R10
R11
R12
OE
R13
NC
R14
OP
5D3
OP
5D2
R15
R16
NC
T1
NC
T2
OP
2D3
OP
2D1
OP
4D2
OP
6D3
OP
6D0
OFRM
2
OFRM
7
OCLK
2
OCLK
5
T3
T4
T5
T6
T7
T8
T9
T10
T11
C T LE N
OP
7D3
OP
7D0
T12
T13
T14
NC
T15
NC
T16
,
NC
NC
OP
2D2
OP
4D3
OP
4D1
OP
6D2
OFRM
0
OFRM
3
OFRM
6
OCLK
1
OCLK
4
OCLK
7
OP
7D2
OP
7D1
NC
NC
3606 drw 04a
Note:
1. All V
CC
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground supply.
3. Package body is approximately 17mm x 17mm x 1.4mm.
5 of 26
March 31, 2001
