High performance 64-bit microprocessor, based on the
RISCore4000
– Minimized branch and load delays, through streamlined
5-stage scalar pipeline.
– Single and double precision floating-point unit
– 125 peak MFLOP/s at 250 MHz
– 330 Dhrystone MIPS at 250 MHz
– Flexible RC4700-compatible MMU
– Joint TLB on-chip, for virtual-to-physical address mapping
x
On-chip two-way set associative caches
– 16KB instruction cache (I-cache)
– 16KB data cache (D-cache)
x
Optional I-cache and D-cache locking (per set), provides
improved real-time support
x
Enhanced, flexible bus interface allows simple, low-cost
design
– 64-bit Bus Interface option, 1000MB/s bandwidth support
– 32-bit Bus Interface option, 500MB/s bandwidth support
– SDRAM timing protocol, through delayed data in write cycles
– RC4000/RC5000 family bus-protocol compatibility
– Bus runs at fraction of pipeline clock (1/2 to 1/8)
x
Implements MIPS-III Instruction Set Architecture (ISA)
x
3.3V core with 3.3V I/O
x
x
RC64474
™
RC64475
™
Software compatible with entire RISController Series of
Embedded Microprocessors
x
Industrial temperature range support
x
Active power management
– Powers down inactive units, through sleep-mode feature
x
100% pin compatibility between RC64574, RC64474 and
RC4640
x
100% pin compatibility between RC64575, RC64475 and
RC4650
x
RC64474 available in 128-pin QFP package, for 32-bit only
systems
x
RC64475 available in 208-pin QFP package, for full 64/32 bit
systems
x
Simplified board-level testing, through full Joint Test Action
Group (JTAG) boundary scan
x
Windows® CE compliant
Block diagram
330 M IPS
64-bit
RISCore4000
CPU Core
System Control
Coprocessor
(CPO)
125 M FLOPS
Single/Double
Precision
FPA
C ontrol B us
D ata B us
Instru ction B us
16KB
Instruction Cache
(Lockable)
32-/64-bit
Synchronized
System
Interface
16KB
Data Cache
(Lockable)
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
1 of 25
2001 Integrated Device Technology, Inc.
April 10, 2001
DSC 4952
RC64474™ RC64475™
Device Overview
1
Extending Integrated Device Technology’s (IDT) RISCore4000 based
choices (see Table 1), the RC64474 and RC64475 are high perfor-
mance 64-bit microprocessors targeted towards applications that require
high bandwidth, real-time response and rapid data processing and are
ideal for products ranging from internetworking equipment (switches,
routers) to multimedia systems such as web browsers, set-top boxes,
video games, and Windows
®
CE based products. These processors are
rated at 330 Dhrystone MIPS and 125 Million floating point operations
per second, at 250 MHz. The internal cache bandwidth for these devices
is over 3GB/second. The 64-bit external bus bandwidth is at more than
1000MB/s, and the 32-bit external bus bandwidth is at 500MB/s.
The RC64474 is packaged in a 128-pin QFP footprint package and
uses a 32-bit external bus, offering the ideal combination of 64-bit
processing power and 32-bit low-cost memory systems. The RC64475
is packaged in a 208-pin QFP footprint package and uses the full 64-bit
external bus. The RC64475 is ideal for applications requiring 64-bit
performance and 64-bit external bandwidth.
IDT’s RISCore4000
is a 250MHz 64-bit execution core that uses a
5-stage pipeline, eliminating the “issue restrictions” associated with
other more complex pipelines. The RISCore4000 implements the
MIPS-III Instruction Set Architecture (ISA) and is upwardly compatible
with applications that run on earlier generation parts.
Implementation of the MIPS-III architecture results in 64-bit opera-
tions, improved performance for commonly used code sequences in
Detailed system operation information is provided in the RC64474/RC64475
user’s manual.
1.
operating system kernels, and faster execution of floating-point intensive
applications.
The
RISCore4000 integer unit
implements a load/store architecture
with single cycle ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The ALU consists of the integer adder
and logic unit. The adder performs address calculations in addition to
arithmetic operations, and the logic unit performs all of the processor’s
logical and shift operations. Each unit is highly optimized and can
perform an operation in a single pipeline cycle. Both 32- and 64-bit data
operations are performed by the RISCore4000, utilizing 32 general
purpose 64-bit registers (GPR) that are used for integer operations and
address calculation. A complete on-chip floating-point co-processor
(CP1), which includes a floating-point register file and execution units,
forms a “seamless” interface, decoding and executing instructions in
parallel with the integer unit.
CP1’s floating-point execution units
support both single and
double precision arithmetic—as specified in the IEEE Standard 754—
and are separated into a multiply unit and a combined add/convert/
divide/square root unit. Overlap of multiplies and add/subtract is
supported, and the multiplier is partially pipelined, allowing the initiation
of a new multiply instruction every fourth pipeline cycle.
The
floating-point register file
is made up of thirty-two 64-bit regis-
ters. The floating-point unit can take advantage of the 64-bit wide data
cache and issue a co-processor load or store doubleword instruction in
every cycle. The RISCore4000’s
system control coprocessor (CP0)
registers
are also incorporated on-chip and provide the path through
which the virtual memory system’s page mapping is examined and
changed, exceptions are handled, and any operating mode selections
are controlled.
RISCore4000/RISCore5000 Family of Socket Compatible Processors
32-bit Processors
RC4640
CPU
Performance
FPA
Caches
External Bus
64-bit RISCore4000
w/ DSP extensions
>350MIPS
89 mflops, single pre-
cision only
8kB/8kB, 2-way, lock-
able by set
32-bit
64-bit Processors
RC64574
RC4650
64-bit RISCore4000
w/ DSP extensions
>350MIPS
89 mflops, single pre-
cision only
8kB/8kB, 2-way, lock-
able by set
32- or 64-bit
RC64474
64-bit RISCore4000
>330MIPS
125 mflops, single and
double precision
16kB/16kB, 2-way,
lockable by set
32-bit, Superset pin
compatible w/RC4640
3.3V
180-250 MHz
128 QFP
96 page TLB
Cache locking, JTAG,
syncDRAM mode, 32-
bit external bus
RC64475
64-bit RISCore4000
>330MIPS
125 mflops, single
and double precision
16kB/16kB, 2-way,
lockable by set
32-or 64-bit, Super-
set pin compatible w/
RC4650
3.3V
180-250 MHz
208 QFP
96 page TLB
Cache locking, JTAG,
syncDRAM mode, 32-
64- bit bus option
RC64575
64-bit RISCore5000
w/ DSP extensions
>440MIPS
666 mflops, single
and double precision
32kB/32kB, 2-way,
lockable by line
32-or 64-bit, Super-
set pin compatible w/
RC4650, RC64475
2.5V
200-333 MHz
208 QFP
96 page TLB
Cache locking, JTAG,
syncDRAM mode, 32-
64- bit bus option
64-bit RISCore5000 w/
DSP extensions
>440MIPS
666 mflops, single and
double precision
32kB/32kB, 2-way,
lockable by line
32-bit, Superset pin
compatible w/RC4640,
RC64474
2.5V
200-333 MHz
128 QFP
96 page TLB
Cache locking, JTAG,
syncDRAM mode, 32-
bit external bus
Voltage
Frequencies
Packages
MMU
Key Features
3.3V
100-267 MHz
128 PQFP
Base-Bounds
Cache locking, on-
chip MAC, 32-bit
external bus
3.3V
100-267 MHz
208 QFP
Base-Bounds
Cache locking, on-
chip MAC, 32-bit & 64
bit bus option
Table 1 RISCore4000/RISCore5000 Processor Family
2 of 25
April 10, 2001
RC64474™ RC64475™
A secure user processing environment is provided through the
user,
supervisor, and kernel operating modes
of virtual addressing to
system software. Bits in a status register determine which of these
modes is used.
If configured for 64-bit
virtual addressing,
the virtual address space
layout becomes an upwardly compatible extension of the 32-bit virtual
address space layout. Figure 1 is an illustration of the address space
layout for the 32-bit virtual address operation.
can be locked into the TLB and avoid being randomly replaced, which
facilitates the design of real-time systems, by allowing deterministic
access to critical software.
The TLB also contains information to control the cache coherency
protocol, and cache management algorithm for each page. However,
hardware-based cache coherency is not supported.
The RC64474 and RC64475 enhance IDT’s entire RISCore4000
series through the implementation of features such as boundary scan, to
facilitate board level testing; enhanced support for SyncDRAM, to
simplify system implementation and improve performance.
The RC64474/475 processors offer a
direct migration path
for
designs based on IDT’s RC4640/RC4650 processors
2
, through full pin
and socket compatibility. Also, full 64-bit-family software and bus-
protocol compatibility ensures the RC64474/475 access to a robust
development tools infrastructure, allowing quicker time to market.
Development Tools
An array of hardware and software tools is available to assist system
designers in the rapid development of RC64474/475 based systems.
This accessibility allows a wide variety of customers to take full advan-
tage of the device’s high-performance features while addressing today’s
aggressive time-to-market demands.
0xFFFFFFFF
0xE0000000
0xDFFFFFFF
Kernel virtual address space
(kseg3)
Mapped, 0.5GB
Supervisor virtual address space
(sseg)
Mapped, 0.5GB
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0xC0000000
0xBFFFFFFF
0xA0000000
0x9FFFFFFF
0x80000000
0x7FFFFFFF
Cache Memory
To keep the RC64474 and RC64475’s high-performance pipeline full
and operating efficiently, on-chip instruction and data caches have been
incorporated. Each cache has its own data path and can be accessed in
the same single pipeline clock cycle.
The 16KB two-way set associative
instruction cache (I-cache)
is
virtually indexed, physically tagged, and word parity protected. Because
this cache is virtually indexed, the virtual-to-physical address translation
occurs in parallel with the cache access, further increasing performance
by allowing both operations to occur simultaneously. The instruction
cache provides a peak instruction bandwidth of 1000MB/sec at 250MHz.
The 16KB two-way set associative
data cache (D-cache)
is byte
parity protected and has a fixed 32-byte (eight words) line size. Its tag is
protected with a single parity bit. To allow simultaneous address transla-
tion and data cache access, the D-cache is virtually indexed and physi-
cally tagged. The data cache can provide 8 bytes each clock cycle, for a
peak bandwidth of 2GB/sec.
To lock critical sections of code and/or data into the caches for quick
access, a
“cache locking”
feature has been implemented. Once
enabled, a cache is said to be locked when a particular piece of code or
data is loaded into the cache and that cache location will not be selected
later for refill by other data. This feature locks a set (8KB) of Instructions
and/or Data.
Table 2 lists the RC64474/475 Instruction and data cache attributes.
To ensure socket compatibility, refer to Table 8 and Table 9 at back of data
The S3C2440A memory controller provides memory control signals that are required for external memory access. The S3C2440A has the following features: Little/Big endian ( selectable by a software) Ad...[详细]
5月初，据赛诺数据， vivo 旗舰机X21上市前五周表现，超过 vivo X9s，这意味着，X21延续了 vivo X系列机型态势。在华为P20、小米Mix 2S等同档位新机紧逼局势下，X21成为国产手机中3000-4000元段位线下市场份额领先机型。下面就随手机便携小编一起来了解一下相关内容吧。 赛诺数据：vivo站稳3000-4000元档位智能机 从2016年开始，...[详细]
FPGA/CPLD
