IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
BUS-INTERFACE FLIP-
FLOP WITH 3-STATE OUT-
PUTS AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
IDT74ALVCH16823
FEATURES:
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
This 18-bit bus-interface flip-flop is built using advanced dual metal CMOS
technology. The ALVCH16823 features 3-state outputs designed specifically
for driving highly capacitive or relatively low-impedance loads. The device is
particularly suitable for implementing wider buffer registers, I/O ports, bidirec-
tional bus drivers with parity, and working registers.
The ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop.
With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the
low-to-high transitions of the clock. Taking
CLKEN
high disables the clock buffer,
thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs
to go low independently of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs
in either a normal logic state (high or low logic levels) or a high-impedance state.
In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components. The
OE
input does not affect the internal operation of the flip-flops. Old data can be
retained or new data can be entered while the outputs are in the high-impedance
state.
The ALVCH16823 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16823 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistor.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
1
OE
2
2
OE
27
1
CLR
1
2
CLR
28
1
CLKEN
55
CE
R
3
2
CLKEN
30
CE
R
15
1
CLK
1
D
1
56
54
C
1
D
1
1
Q
1
2
CLK
2
D
1
29
42
C
1
D
1
2
Q
1
TO 8 OTHER CHANNELS
TO 8 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4237/2
IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
CLR
1
OE
1
Q
1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
CLK
1
CLKEN
1
D
1
Unit
V
V
°C
mA
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
GND
1
Q
2
1
Q
3
GND
1
D
2
1
D
3
V
CC
1
Q
4
1
Q
5
1
Q
6
V
CC
1
D
4
1
D
5
1
D
6
GND
1
Q
7
1
Q
8
1
Q
9
2
Q
1
2
Q
2
2
Q
3
GND
1
D
7
1
D
8
1
D
9
2
D
1
2
D
2
2
D
3
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
NOTE:
1. As applicable to the device type.
GND
2
Q
9
2
OE
2
CLR
GND
2
D
9
2
CLKEN
2
CLK
FUNCTION TABLE
(EACH 9-BIT FLIP-FLOP)
(1)
Inputs
xOE
L
L
L
L
L
H
xCLR
L
H
H
H
H
X
xCLKEN
X
L
L
L
H
X
xCLK
X
↑
↑
L
X
X
xDx
X
H
L
X
X
X
Output
xQx
L
H
L
Q
0(2)
Q
0(2)
Z
TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xDx
xCLK
xCLKEN
xQx
xOE
xCLR
Data Inputs
(1)
Clock Input
Clock Enable Inputs
3-State Outputs
3-State Output Enable Inputs
Clear Inputs
Description
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
3
IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
27
16
V
CC
= 3.3V ± 0.3V
Typical
30
18
Unit
pF
4
IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
W
t
SU
t
SU
t
SU
t
SU
t
H
t
H
t
H
t
SK(O)
Propagation Delay
xCLK to xQx
Propagation Delay
xCLR
to xQx
Output Enable Time
xOE
to xQx
Output Disable Time
xOE
to xQx
Pulse Duration,
xCLR
LOW
Pulse Duration, xCLK HIGH or LOW
Set-up Time,
xCLR
inactive
Set-up Time, data LOW before xCLK↑
Set-up Time, data HIGH before xCLK↑
Set-up Time,
xCLKEN
LOW before xCLK↑
Hold Time, data LOW after xCLK↑
Hold Time, data HIGH after xCLK↑
Hold Time,
xCLKEN
LOW after CLK↑
Output Skew
(2)
3.3
3.3
0.7
1.4
1.1
1.8
0.4
0.7
0.2
—
—
—
—
—
—
—
—
—
—
—
3.3
3.3
0.7
1.6
1.1
1.9
0.5
0.1
0.3
—
—
—
—
—
—
—
—
—
—
—
3.3
3.3
0.8
1.3
1
1.5
0.5
0.8
0.4
—
—
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1.1
5.4
—
4.7
1.3
4.5
ns
1
6
—
5.7
1
4.8
ns
1
5.4
—
5.2
1.2
4.6
ns
Parameter
Min.
150
1
Max.
—
5.8
V
CC
= 2.7V
Min.
150
—
Max.
—
5.2
V
CC
= 3.3V ± 0.3V
Min.
150
1
Max.
—
4.5
Unit
MHz
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
5
