IDTCV174C
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV174C
FEATURES:
DESCRIPTION:
• Compliant with Intel CK505
• Power management control suitable for low power applications
• One high precision PLL for CPU/SRC/PCI, SSC and N program-
ming
• One high precision PLL for SRC/PCI, SSC and N programming
• One high precision PLL for 96MHz/48MHz
• Push-pull IOs for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength
• Smooth transition for N programming
• Available in SSOP and TSSOP packages
IDTCV174C is a 56 pin clock device, incorporating Intel CK505 requirements
for the Intel advance P4 processor. The CPU output buffer is designed to
support up to 400MHz reference clock for the CPU. This chip has three PLLs
inside for CPU, SRC/PCI and 48MHz/DOT96 IO clocks.
OUTPUTS:
•
•
•
•
•
•
•
•
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 500ps
2*0.7V differential CPU CLK pair
7*0.7V differential SRC CLK pair
One CPU_ITP/SRC differential clock pair
One SRC0/DOT96 differential clock pair
6*PCI, 33.3MHz
1*48MHz
1*REF
1*SATA
FUNCTIONAL BLOCK DIAGRAM
REF
XTAL_IN
CPU[1:0]
CPU, SRC, PCI
Output Buffer
Stop Logic
XTAL
Osc Amp
XTAL_OUT
PLL1
SSC
N Programmable
CPU_ITP/SRC8
SDATA
SCLK
SM Bus
Controller
PLL3
SSC
N Programmable
SRC CLK
Output Buffer
Stop Logic
SRC[7:1]
PCI[4:0], PCIF5
SATA
CKPRWGD/PD#
CPU_STOP#
PCI_STOP#
SRC5_EN, LTE
ITP_EN
CR#_[F:A]
FSC,B,A
Control
Logic
48MHz
Fixed PLL
PLL2
48MHz/96MHz
Output BUffer
DOT96/SRC0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2005 Integrated Device Technology, Inc.
MAY 2006
DSC 6898/8
IDTCV174C
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
PCI0/CR#_A
V
DD
_PCI
PCI1/CR#_B
PCI2//LTE
PCI3
PCI4/SRC5_EN
PCIF5/ITP_EN
V
SS
_PCI
V
DD
_48MHz
USB_48/FSA
V
SS
_48MHz
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
SCL
SDA
REF/FSC/TEST_SEL
V
DD
_REF
XTAL_IN
XTAL_OUT
V
SS
_REF
FSB/TEST_MODE
CKPWRGD/PD#
V
DD
_CPU
CPUT0
CPUC0
V
SS
_CPU
CPUT1
V
DD
_IO
SRCT0/DOT96T
SRCC0/DOT96C
V
SS
_IO
CPUC1
V
DD
_CPU_IO
IO_V
OUT
V
DD
_PLL3
SRCT1/SE1
SRCC1/SE2
V
SS
_PLL3
V
DD
_PLL3_IO
SATAT/SRCT2
SATAC/SRCC2
V
SS
_SRC
SRCT3/CR#_C
SRCC3/CR#_D
V
DD
_SRC_IO
SRCT4
SRCC4
SRCT8/CPU_ITPT
SRCC8/CPU_ITPC
V
DD
_SRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
V
SS
_SRC
SRCT6
SRCC6
V
DD
_SRC
PCI_STOP#/SRCT5
CPU_STOP#/SRCC5
TSSOP
TOP VIEW
2
IDTCV174C
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
PCI0/CR#_A
V
DD
_PCI
PCI1/CR#_B
PCI2/LTE
PCI3
PCI4/SRC5_EN
PCIF5/ITP_EN
V
SS
_PCI
V
DD
_48
USB 48/FS_A
V
SS
_48
V
DD
_IO
SRCT0/DOT96T
SRCC0/DOT96C
V
SS
_IO
V
DD
_PLL3
SRCT1/SE1
SRCC1/SE2
V
SS
_PLL3
V
DD
_PLL3_IO
SRCT2/SATAT
SRCC2/SATAC
V
SS
_SRC
SRCT3/CR#_C
SRCC3/CR#_D
V
DD
_SRC_IO
SRCT4
SRCC4
CPU_Stop#/SRCC5
PCI_Stop#/SRCT5
V
DD
_SRC
SRCC6
SRCT6
V
SS
_SRC
SRCC7/CR#_E
SRCT7/CR#_F
V
DD
_SRC_IO
SRCC8/CPU_ ITPC
SRCT8/CPU_ ITPT
IO_V
OUT
Type
I/O
PWR
I/O
I/O
OUT
I/O
I/O
GND
PWR
I/O
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
I/O
I/O
PWR
OUT
OUT
I/O
I/O
PWR
OUT
OUT
GND
I/O
I/O
PWR
OUT
OUT
OUT
Description
33.33MHz/SRC0, 2 Differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode is selected
by SMBus control register. Default is PCI clock mode
3.3V
33.33MHz/SRC1, 2 Differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode is selected
by SMBus control register. Default is PCI clock mode
33.33MHz. High = overclocking disabled. Power-on latch.
33.33MHz
33.33MHz. Pin 29, 30 mode selection. Power on latch, high = SRC5, low = CPU and PCI Stop#
33.33MHz. Pin 38, 39 mode selection. Power on latch, high = CPU_ITP, low = SRC8
GND
3.3V
48MHz/ Frequency select, power on latch
GND
0.8V
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0
GND
3.3V
Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1.
Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1
GND
0.8V
Differential output clock
Differential output clock
GND
SRC clock/ SRC differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode selected by
SMBus control register. Default is SRC3.
SRC clock/ SRC differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode selected by
SMBus control register. Default is SRC3..
0.8V
Differential output clock
Differential output clock
CPU stop, low = stop/ SRC clock. Mode selected by pin6, SRC5_EN.
PCI stop, low = stop/ SRC clock. Mode selected by pin6, SRC5_EN.
3.3V
Differential output clock
Differential output clock
GND
SRC clock/ SRC differential clock output enable, control SRC6, 0 = enable. Mode selected by SMBus control
register. Default is SRC7.
SRC clock/ SRC differential clock output enable, control SRC8, 0 = enable. Mode selected by SMBus control
register. Default is SRC7.
0.8V
SRC clock/CPU clock. Mode selected by pin7.
SRC clock/CPU clock. Mode selected by pin7.
V_IO adjustment
3
IDTCV174C
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION, CONTINUED
Pin #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Name
V
DD
_CPU_IO
CPUC1
CPUT1
V
SS
_CPU
CPUC0
CPUT0
V
DD
_CPU
CKPWRGD/PD#
FS_B/TestMode
V
SS
_REF
XTAL_OUT
XTAL_IN
V
DD
_REF
REF/FS_C/TestSel
SDA
SCL
Type
PWR
OUT
OUT
GND
OUT
OUT
PWR
IN
IN
GND
OUT
IN
PWR
I/O
I/O
IN
Description
0.8V
Differential output clock
Differential output clock
GND
Differential output clock
Differential output clock
3.3V
CKPWRGD power good, active LOW, used to latch FSA,B,C, ITP_EN, TME, and SRC5_EN , active HIGH.
After, becomes power down, LOW active.
Frequency Select at CKPWRGD assertion. Test Mode selection, see TEST_MODE selection table
GND
XTAL out
XTAL in
3.3V
14.318MHz. Frequency Select at CKPWRGD assertion. Selects test mode if pulled above 2V at CKPWRGD
assertion.
SMBus clock
SMBus data
TEST MODE SELECTION
(1)
Test_Mode
1
0
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
If TEST_SEL sampled above 2V at CKPWRGD active LOW
PCI/F
REF/N
Hi-Z
REF
REF
Hi-Z
DOT_96/DOT_SSC
REF/N
Hi-Z
USB
REF/N
Hi-Z
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, with V
IH
_FS and V
IL
_FS threshoulds.
FREQUENCY SELECTION
FSC, B, A
101
001
011
010
000
100
110
111
CPU
100
133
166
200
266
333
400
Reserve
SRC[7:0]
100
100
100
100
100
100
100
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
48
48
48
48
48
48
48
DOT
96
96
96
96
96
96
96
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
4
IDTCV174C
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDA
V
DD
T
STG
T
AMBIENT
T
CASE
ESD Prot
Description
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RESOLUTION
Unit
V
V
°C
°C
°C
V
CPU
CPU
CPU
CPU
CPU
CPU
CPU
SRC
= 100MHz
= 133MHz
= 166MHz
= 200MHz
= 266MHz
= 333MHz
= 400MHz
= 100MHz
N Resolution (MHz)
0.500000
0.666667
0.666667
1.000000
1.333333
1.333333
2.000000
0.500000
%
0.5%
0.5%
0.4%
0.5%
0.5%
0.4%
0.5%
0.5%
N=
200
200
250
200
200
250
200
200
Min
Max
4.6
4.6
+150
+70
+115
–65
0
2000
SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
INDEX BLOCK READ PROTOCOL
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Description
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit 30-37).
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
bytes)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
Master
Slave
Master
5
