18Mb Pipelined
DDR™II SIO SRAM
Burst of 2
Features
◆
◆
IDT71P79204
IDT71P79104
IDT71P79804
IDT71P79604
Description
The IDT DDRII
TM
Burst of two SIO SRAMs are high-speed syn-
chronous memories with independent, double-data-rate (DDR), read
and write data ports with two data items passed with each read or write.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the DDRII SIO are unidirectional and can be optimized
for signal integrity at very high bus speeds. Memory bandwidth is higher
than DDR SRAM with bi-directional data buses as separate read and
write ports eliminate bus turn around cycle. Separate read and write
ports also enable easy depth expansion. Each port can be selected
independantly with a R/W input shared among all SRAMs and provide
a new
LD
load control signal for each bank. The DDRII SIO has scal-
able output impedance on its data output bus and echo clocks, allowing
the user to tune the bus for low noise and high performance.
The DDRII SIO has a single SDR address bus with multiplexed
read and write addresses. The read/write and load control inputs are
received on the first half of the clock cycle. The byte and nibble write
signals are received on both halves of the clock cycle simultaneously
with the data they are controlling on the data input bus.
The DDRII SIO has echo clocks, which provide the user with a
clock that is precisely timed to the data output, and tuned with matching
impedance and signal quality. The user can use the echo clock for
downstream clocking of the data. Echo clocks eliminate the need for the
user to produce alternate clocks with precise timing, positioning, and
signal qualities to guarantee data capture. Since the echo clocks are
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
Separate, Independent Read and Write Data Ports
- Supports concurrent transactions
◆
Dual Echo Clock Output
◆
2-Word Burst on all SRAM accesses
◆
Multiplexed Address Bus
- One Read or one Write request per clock cycle
◆
DDR (Double Data Rate) Data Bus
- Two word burst data per clock
◆
Depth expansion through Control Logic
◆
HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V
to 1.9V.
◆
Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70 ohms
◆
1.8V Core Voltage (V
DD
)
◆
165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package
◆
JTAG Interface
Functional Block Diagram
(Note1)
D
DATA
REG
DATA
REG
(Note1)
WRITE DRIVER
SA
LD
R/W
BWx
(Note3)
CTRL
LOGIC
18M
MEMORY
ARRAY
(Note4)
(Note4)
OUTPUT SELECT
(Note2)
SENSE AMPS
OUTPUT REG
ADD
REG
(Note2)
WRITE/READ DECODE
(Note1)
Q
K
K
C
C
CLK
GEN
SELECT OUTPUT CONTROL
CQ
CQ
6432 drw 16
Notes:
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the
BW
is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
NOVEMBER 2005
1
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6432/01
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
generated by the same source that drives the data output, the relation-
ship to the data is not significantly affected by voltage, temperature and
process, as would be the case if the clock were generated by an outside
source.
All interfaces of the DDR II SIO are HSTL, allowing speeds beyond
SRAM devices that use any form of TTL interface. The interface can be
scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if
necessary. The device has a V
DDQ
and a separate Vref, allowing the
user to designate the interface operational voltage, independent of the
device core voltage of 1.8V V
DD
. The output impedance control allows
the user to adjust the drive strength to adapt to a wide range of loads and
transmission lines.
Clocking
The DDRII SIO SRAM has two sets of input clocks, namely the K,
K
clocks and the C,
C
clocks. In addition, the DDRII SIO has an output
“echo” clock, CQ,
CQ.
The K and
K
clocks are the primary device input clocks. The K
clock is, used to clock in the control signals (LD, R/W and
BWx
or
NWx),
the address, and the first word of the data burst during a write operation.
The
K
clock is used to clock in the control signals (BWx or
NWx)
and the
second word of the data burst during a write operation. The K and
K
clocks are also used internally by the SRAM. In the event that the user
disables the C and
C
clocks, the K and
K
clocks will also be used to clock
the data out of the output register and generate the echo clocks.
The C and
C
clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C
must be presented to the SRAM within the timing tolerances. The
output data from the DDRII SIO will be closely aligned to the C and
C
input, through the use of an internal DLL. When C is presented to the
DDRII SIO SRAM, the DLL will have already internally clocked the data
to arrive at the device output simultaneously with the arrival of the
C
clock. The C and second data item of the burst will also correspond.
Single Clock Mode
The DDRII SIO SRAM may be operated with a single clock pair. C
and
C
may be disabled by tying both signals high, forcing the outputs
and echo clocks to be controlled instead by the K and
K
clocks.
DLL Operation
The DLL in the output structure of the DDRII SIO SRAM can be
used to closely align the incoming clocks C and
C
with the output of the
data, generating very tight tolerances between the two. The user may
disable the DLL by holding
Doff
low. With the DLL off, the C and
C
(or
K and
K
if C and
C
are not used) will directly clock the output register of
the SRAM. With the DLL off, there will be a propagation delay from the
time the clock enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ and
CQ,
are generated by the C and
C
clocks
(or K,
K
if C,
C
are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of
CQ.
The rising edge of
C
generates
the rising edge of
CQ
and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
DDRII SIO devices internally store the two words of the burst as a
single wide word and the words will retain their burst order. There is no
ability to address an individual word level in a burst, as is possible in the
DDRII common I/O devices. The byte and nibble write signals can be
used to prevent writing to any individual bytes, or combined to prevent
writing word(s) of the burst.
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and
C
clocks.
Write operations are initiated by holding the Read/Write control input
(R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the two
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BWx or
NWx)
inputs. On the
following rising edge of
K,
the second half of the data write burst will be
accepted at the device input with the designated (BWx or
NWx)
inputs.
Output Enables
The DDRII SIO SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with V
DDQ
= 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to V
DDQ
.
6.42
2
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Definitions
Symbol
Pin Function
Description
Data input signals, sampled on the rising edge of K and
K
clocks during valid write operations
2M x 8 -- D[7:0]
2M x 9 -- D[8:0]
1M x 18 -- D[17:0]
512K x 36 -- D[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising
edge of
K
clocks during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same
edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and
not written in to the device.
2M x 9 --
BW
0
controls DQ[8:0]
1M x 18 --
BW
0
controls DQ[8:0] and
BW
1
controls DQ[17:9]
512K x 36 --
BW
0
controls DQ[8:0],
BW
1
controls DQ[17:9],
BW
2
controls DQ[26:18] and
BW
3
controls DQ[35:27]
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.
Sampled on the rising edge of the K and
K
clocks during write operations. Used to select which nibble is written
into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the
nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the
corresponding nibble of data to be ignored and not written in to the device.
2M x 8--NW0 controls D[3:0] and
NW1
controls D[7:4]
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on
the rising edge of both the C and
C
clocks during Read operations or K and
K
when operating in single clock
mode. When the Read port is deselect ed, Q[X:0] are automatically three-stated.
Load Control Logic. Sampled on the rising edge of K. If
LD
is low, a two word burst read or write operation will
be initiated as designated by the R/W input. If
LD
is high during the rising edge of K, operations in progress will
complete, but new operations will not be initiated.
Read or Write Control Logic. If
LD
is low during the rising edge of K, the R/W indicates whether a new operation
should be a read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be
initiated. If the
LD
input is high during the rising edge of K, the R/W input will be ignored.
Positive Output Clock Input. C is used in conjunction with
C
to clock out the Read data from the device. C and
C
can be used together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
Negative Output Clock Input.
C
is used in conjunction with C to clock out the Read data from the device. C and
C
can be used together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive
out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
Negative Input Clock Input.
K
is used to capture synchronous inputs being presented to the device and to drive
out data through Q[X:0] when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data
outputs and can be used as a data valid indication. These signals are free running and do not stop when the
output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and
ground. Alternately, this pin can be connected directly to V
DDQ
, which enables the minimum impedance mode.
This pin cannot be connected directly to GND or left unconnected.
6432 tbl 02a
D[X:0]
Input
Synchronous
BW
0
,
BW
1
BW
2
,
BW
3
Input
Synchronous
NW0 NW1
Input
Synchronous
SA
Input
Synchronous
Output
Synchronous
Input
Synchronous
Input
Synchronous
Q[X:0]
LD
R/W
C
Input Clock
C
Input Clock
K
K
Input Clock
Input Clock
CQ,
CQ
Output Clock
ZQ
Input
6.42
3
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Definitions continued
Symbol
Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL
turned off will be different from those listed in this data sheet. There will be an increased propagation delay
from the incidence of C and
C
to Q, or K and
K
to Q as configured. The propagation delay is not a tested
parameter, but will be similar to the propagation delay of other SRAM devices in this speed grade.
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to V
DD
when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to V
DD
when the pin is unconnected.
No connects inside the package. Can be tied to any voltage level.
Input
Reference
Power
Supply
Ground
Power
Supply
Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well
as AC measurement points.
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground for the device. Should be connected to ground of the system.
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or
scaled to the desired output voltage.
6432 tbl 02b
Doff
Input
TDO
TCK
TDI
TMS
NC
V
REF
V
DD
V
SS
V
DDQ
Output
Input
Input
Input
6.42
4
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79204 (2M x 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS/
SA
(2)
NC
NC
D
4
NC
NC
D
5
V
REF
NC
NC
Q
6
NC
D
7
NC
TCK
3
SA
NC
NC
NC
Q
4
NC
Q
5
V
DDQ
NC
NC
D
6
NC
NC
Q
7
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
NW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS/
SA
(1)
NC
NC
NC
D
2
NC
NC
V
REF
Q
1
NC
NC
NC
NC
NC
TMS
11
CQ
Q
3
D
3
NC
Q
2
NC
NC
ZQ
D
1
NC
Q
0
D
0
NC
NC
TDI
6432 tbl 12
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
