LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND
Q
5
V
DD
RST
FEEDBACK
REF_SEL
SYNC
0
AV
DD
NC
AGND
SYNC
1
FREQ_SEL
GND
Q
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
QSOP
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Q
4
GND
RST
V
DD
V
DD
2xQ
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
PLL_EN
GND
Q
1
V
DD
FEEDBACK
REF_SEL
SYNC
0
AV
DD
NC
AGND
SYNC
1
5
6
7
8
9
10
11
4
3
2
1
28
Q
4
27
26
25
24
23
22
21
20
19
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
12
FREQ_SEL
13
GND
14
Q
0
15
V
DD
16
Q
1
17
GND
18
PLL_EN
PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Max
Supply Voltage to Ground
DC Input Voltage V
IN
AC Input Voltage (pulse width
≤
20ns)
Maximum Power Dissipation (T
A
= 85°C)
T
STG
Storage Temperature Range
–0.5 to +7
–0.5 to +7
–3
1.2
–65 to +150
Unit
V
V
V
W
°C
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, V
IN
= 0V)
QSOP
Parameter
C
IN
C
OUT
Typ.
3
7
Max.
4
9
Typ.
4
8
PLCC
Max.
6
10
Unit
pF
pF
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2
2xQ
V
DD
Q
5
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names
SYNC
0
SYNC
1
REF_SEL
FREQ_SEL
FEEDBACK
Q
0
-Q
4
Q
5
2xQ
Q/2
LOCK
RST
PLL_EN
NC
I/O
I
I
I
I
I
O
O
O
O
O
I
I
—
Reference clock input
Reference clock input
Reference clock select. When 1, selects SYNC
1
. When 0, selects SYNC
0
.
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency
relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in frequency, but inverted with respect to Q.
Clock output. Matched in phase, but frequency is double the Q frequency.
Clock output. Matched in phase, but frequency is half the Q frequency.
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs.
Asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled (normal
operation).
PLL enable. When 1, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes).
No Connection
Description
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= –40°C to +85°C, AV
DD
/
V
DD
= 5V ± 5%
Symbol
F
2XQ
F
Q
F
Q/2
Description
Max Frequency, 2xQ output
Max Frequency, Q
0
- Q
4
, Q
5
outputs
Max Frequency, Q/2 output
– 70
70
35
17.5
– 100
100
50
25
– 132
132
66
33
Units
MHz
MHz
MHz
3
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
SYNC (MHz)
FREQ_SEL
1
1
1
1
0
0
0
0
Output Used for
Feedback
Q/2
Q
0
-Q
4
Q
5
2xQ
Q/2
Q
0
-Q
4
Q
5
2xQ
(allowable range)
Min.
Max
14
28
28
56
7
14
14
28
F
2XQ
/
4
F
2XQ
/
2
F
2XQ
/
2
F
2XQ (1)
F
2XQ
/
8
F
2XQ
/
4
F
2XQ
/
4
F
2XQ
/
2
Q/
2
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
Output Frequency Relationships
Q
5
Q Outputs
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
SYNC X 2
SYNC
– SYNC
SYNC / 2
SYNC X 2
SYNC
– SYNC
SYNC / 2
2XQ
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
NOTE:
1. For the –132 speed grade, maximum input frequency is restricted to 100MHz.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, A
VDD
/V
DD
= 5V ± 5%
Symbol
V
IH
V
IL
V
OH
V
OL
I
OZ
I
IN
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Output HIGH Voltage
Output LOW Voltage
Output Leakage Current
Input Leakage Current
Test Conditions
Guaranteed Logic HIGH level
Guaranteed Logic LOW level
V
DD
= Min., I
OH
=
−24mA
(1)
V
DD
= Min., I
OH
=
−100μA
V
DD
= Min., I
OL
= 24mA
(1)
V
DD
= Min., I
OL
= 100μA
V
OUT
= V
DD
or GND, V
DD
= Max.
V
IN
= AV
DD
or GND, AV
DD
= Max.
Min.
2
—
2.4
3
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
Max.
—
0.9
—
—
0.55
0.2
±5
±5
μA
μA
V
Unit
V
V
V
NOTE:
1. I
OL
and I
OH
are 12mA and –12mA, respectively, for the LOCK output.
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Input Power Supply Current per TTL Input HIGH
(2)
Dynamic Power Supply Current
V
DD
= Max
Test Conditions
(1)
V
DD
= Max., V
IN
= 3.4V
Typ.
0.4
—
Max.
1.5
0.4
Unit
mA
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. This specification does not apply to the PLL_EN input.
4
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
F
I
t
PWC
D
H
Description
Maximum input rise and fall times, 0.8V to 2V
Input Clock Frequency, SYNC
0
, SYNC
1 (1)
Input clock pulse, HIGH or LOW
Duty cycle, SYNC
0
, SYNC
1
Min.
—
14
2
25
Max.
3
F
2XQ
—
75
Unit
ns
MHz
ns
%
NOTE:
1. The F
I
specification is based on Q output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations.
SWITCHING CHARACTERISTICS
(1)
Symbol
t
SKR
t
SKF
t
SKALL
t
PW
t
PW
t
J
t
PD
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Parameter
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/2
(1)
Output Skew Between Falling Edges, Q
0
-Q
4
(1)
Output Skew, All Outputs
(1)
Pulse Width, Q
5,
2xQ outputs
Pulse Width, Q
0
-Q
4
, Q/2 outputs
(1)
Cycle-to-Cycle Jitter, 33MHz
(3)
SYNC Input to Feedback Delay, 28MHz
SYNC Input to Feedback Delay, 33MHz, 50Ω to 1.5V
SYNC to Phase Lock
Output Enable Time,
RST
LOW to HIGH
(2)
Output Disable Time,
RST
HIGH to LOW
(2)
Output Rise/Fall Times, 0.8V to 2V
Min.
—
—
—
T
CY
/2
−
0.65
T
CY
/2
−
0.5
—
−
100
−
100
—
0
0
0.4
Max.
350
350
500
T
CY
/2 + 0.65
T
CY
/2 + 0.5
0.25
400
400
10
7
6
1.5
Unit
ps
ps
ps
ns
ns
ns
ps
ps
ms
ns
ns
ns
NOTES:
1. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
2. Measured in open loop mode PLL_EN = 0.
3. Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FREQUENCY SELECTION TABLE for information
on proper FREQ_SEL level for specified input frequencies.
