MULTI-ISSUE
64-BIT MICROPROCESSOR
Integrate d Device Technology, Inc.
IDT RC5000
FEATURES
•
Dual issue super-scalar execution core, executing at
high-frequency
- 250 MHz frequency
- Dual issue floating-point ALU operations with other
instruction classes
- Traditional 5-stage pipeline, minimizes load and
branch latencies
- Single cycle repeat rate for most floating point ALU
operations
• High level of performance for a variety of applications
- High-performance 64-bit integer unit achieves 330
dhrystone MIPS (dhrystone 2.1)
- Ultra high-performance floating-point accelerator,
directly implementing single- and double-precision
operations achieves 500mflops
- Extremely large on-chip primary caches
- On-chip secondary cache controller
• Large, efficient on-chip caches
- 32KB Instruction Cache, 32KB Data Cache
- 2-set associative in each cache
- Virtually indexed and physically tagged to minimize
cache flushes
- Write-back and write-through selectable on a per
page basis
- Critical word first cache miss processing
- Supports back-to-back loads and stores in any com-
bination at full pipeline rate
•
•
•
•
•
•
High-performance memory system
- Large primary caches integrated on-chip
- Secondary cache control interface on-chip
- High-frequency 64-bit bus interface runs up to
100MHz
- Aggregate bandwidth of on-chip caches, system
interface of 5GB/s
- High-performance write protocols for graphics and
data communications
MIPS-IV 64-bit ISA for improved computation
- Compound floating-point operations for 3D graphics
and floating-point DSP
- Conditional move operations
Compatible with a variety of operating systems
- Windows™ CE
- Numerous MIPS-compatible real-time operating sys-
tems
Uses input system clock, with processor pipeline
clock multiplied by a factor of 2-8
Large on-chip TLB
Active power management, including use of WAIT
operation
BLOCK DIAGRAM
Phase Lock Loop
Data Set A
Store Buffer
SysAD
Write Buffer
Read Buffer
Data Set B
DBus
Control
Tag
Floating Point Register File
Unpacker/Packer
Floating-point Control
Joint TLB
Coprocessor 0
System/Memory
Control
PC Incrementer
Branch Adder
Instruction TLB Virtual
Program Counter
DVA
IVA
Integer Control
AuxTag
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
ABus
Integer Multiply, Divide
FPIBus
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Instruction Set B
IntIBus
Data Tag A
DTLB Physical
Instruction Select
Integer Instruction Register
FP Instruction Register
Instruction Set A
Floating Point
MAdd,Add,Sub, Cvt
Div, SqRt
The IDT logo is a registered trademark and ORION, R4600, R4640, R4650, R4700, R5000, RV5000, and RISController are trademarks of Integrated Device Technology, Inc. MIPS is a registered
trademark of MIPS Computer Systems, Inc.
COMMERCIAL TEMPERATURE RANGE
©
1998 Integrated Device Technology, Inc.
June, 1998
1
IDT RC5000
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION
Integer Pipeline
The RC5000 is a limited dual-issue machine that
The RC5000 serves many performance critical
embedded applications, such as high-end internet- utilizes a traditional 5-stage integer pipeline. This basic
integer pipeline of the RC5000 is illustrated in Figure 1.
working systems, color printers, and graphics terminals.
The integer instruction execution speed is tabulated
The RC5000 is optimized for high-performance appli-
cations, with special emphasis on system bandwidth and (in number of pipeline clocks) as follows:
floating point operations, through integration of high-
Operation
Latency
Repeat
performance computational units and a high-performance
Load
2
1
memory hierarchy. For this class of application, the result
is a relatively low-cost CPU capable of approximately 330
Store
2
1
Dhrystone MIPS.
MULT/MULTU
8
8
IDT’s objectives in offering the RC5000 include:
DMULT/DMULTU
12
12
• Offering a high performance upgrade path to existing
DIV/DIVU
36
36
embedded customers in the internetworking, office
DDIV/DDIVU
68
68
automation and visualization markets.
Other Integer ALU
1
1
• Providing a significant improvement in the floating-
Branch
2
2
point performance currently available in a moderately
priced MIPS CPU.
Jump
2
2
• Providing improvements in the memory hierarchy of
The RC5000’s short pipeline keeps the load and
desktop systems by using large primary caches and
integrating a secondary cache controller.
branch latencies very low. The caches contain special
• Enabling improvements in performance through the
logic that allows any combination of loads and stores to
use of the MIPS-IV ISA.
execute in back-to-back cycles without requiring pipeline
slips or stalls. (This presumes, of course, that the opera-
Instruction Issue Mechanism
The RC5000 recognizes two general classes of tion does not miss in the cache.)
instructions for multi-issue:
• Floating-point ALU
• All others
These instruction classes are pre-decoded by the
RC5000, as they are brought on-chip. The pre-decoded
information is stored in the instruction cache.
Assuming that there are no pending resource
conflicts, the RC5000 can issue one instruction per class
per pipeline clock cycle. Note that this broad separation of
classes insures that there are no data dependencies to
restrict multi-issue.
However, long-latency resources in either the floating-
point ALU (e.g. DIV or SQRT instructions) or instructions
in the integer unit (such as multiply) can restrict the issue
of instructions. Note that the R5000 does not perform out-
of-order or speculative execution; instead, the pipeline
slips until the required resource becomes available.
There are no alignment restrictions on dual-issue
instruction pairs. The RC5000 fetches two instructions
from the cache per cycle. Thus, for optimal performance,
compilers should attempt to align branch targets to allow
dual-issue on the first target cycle, since the instruction
cache only performs aligned fetches.
Instruction Set Architecture
The RC5000 implements the MIPS-IV 64-bit ISA,
including CP1 and CP1X functional units (and their
instruction set).
2
IDT RC5000
COMMERCIAL TEMPERATURE RANGE
I
0
I
1
I
2
I
3
I
4
1I
2I
1R
1I
2R
2I
1A
1R
1I
2A
2R
2I
1D
1A
1R
1I
2D
2A
2R
2I
1W
1D
1A
1R
1I
2W
2D
2A
2R
2I
1W
1D
1A
1R
2W
2D
2A
2R
1W
1D
1A
•••
•••
•••
one cycle
Key to Figure
1I-1R
Instruction cache access
2I
Instruction virtual to physical address translation
2A-2D
Data cache access and load align
1D
Data virtual to physical address translation
1D-2D
Virtual to physical address translation
2R
Register file read
2R
Bypass calculation
2R
Instruction decode
2R
Branch address calculation
1A
Issue or slip decision
1A-2A
Integer add, logical, shift
1A
Data virtual address calculation
2A
Store align
1A
Branch decision
2W
Register file write
Figure 1. R5000 Integer Pipeline Stages
RC5000 Computational Units
The RC5000 contains the following computational units:
Integer ALU.
The RC5000 implements a full, single-cycle 64-bit ALU for all integer ALU functions other than
multiply and divide. Bypassing is used to support back-to-back ALU operations at the full pipeline rate, without requiring
stalls for data dependencies.
Integer Multiply/Divide Unit.
This unit is separated from the primary ALU, to allow these longer latency operations
to run in parallel with other operations. The pipeline stalls only if an attempt to access the HI or LO registers is made
before the operation completes.
Floating-point ALU.
This unit is responsible for all CP1/CP1X ALU operations other than DIV/SQRT. The unit is
pipelined to allow a single-cycle repeat rate for single-precision operations
Floating-point DIV/SQRT unit.
This unit is separated from the other floating-point ALU, so that these long latency
operations do not prevent the issue of other floating point operations.
In addition, the RC5000 implements separate logical units to implement loads, stores, and branches.
Electrical Specifications
Operating Frequency
The input clock operates in a frequency range of 33MHz to 100MHz. The pipeline frequency for the RC5000 is 2 to
8 times the input clock (up to the maximum for the speed grade of CPU).
THERMAL CONSIDERATIONS
The RC5000 utilizes special packaging techniques, to improve the thermal properties of high-speed processors.
The RC5000 is packaged using cavity down packaging in a 223-pin PGA package with integral thermal slug, and a
272-pin BGA package. These packages effectively dissipate the power of the CPU, increasing device reliability.
3
IDT RC5000
COMMERCIAL TEMPERATURE RANGE
The RC5000 utilizes an all-aluminum package with
the die attached to a normal copper lead frame mounted
to the aluminum casing. Due to the heat-spreading effect
of the aluminum, the package allows for an efficient
thermal transfer between the die and the case. The
aluminum offers less internal resistance from one end of
the package to the other, reducing the temperature
gradient across the package and therefore presenting a
greater area for convection and conduction to the PCB for
a given temperature. Even nominal amounts of airflow will
dramatically reduce the junction temperature of the die,
resulting in cooler operation.
The RC5000 is guaranteed in a case temperature
range of 0° to +85° C. The type of package, speed
(power) of the device, and airflow conditions affect the
equivalent ambient temperature conditions that will meet
this specification.
The equivalent allowable ambient temperature, T
A
,
can be calculated using the thermal resistance from case
to ambient (∅
CA
) of the given package. The following
equation relates ambient and case temperatures:
T
A
= T
C
- P *
∅
CA
where P is the maximum power consumption at hot
temperature, calculated by using the maximum I
CC
speci-
fication for the device. Typical values for
∅
CA
at various
airflows are shown in Table 1.
∅
CA
Airflow (ft/min)
PGA
BGA
0
16
14
200
7
6
400
5
4
600
3
3
800
2.5
2.5
1000
2
2
DATA SHEET REVISION HISTORY
Changes to version dated January 1996:
Pin Description section:
- Corrected pin list for Clock/Control, Initialization,
and Secondary Cache interfaces.
Advance Pin-Out section:
- Changed pins AA19 and AA21 from Vcc to Vss.
Changes to version dated March 1997:
- Upgraded data sheet status from “Preliminary” to
Final.
- Added section on thermal considerations
- Added section on absolute maximum ratings
Changes to version dated June 1997:
- Revised Power Consumption and System Interface
Parameters
Changes to version dated September 1997:
- Added user notation on Boot Mode Bits 20 and 33
for 200 MHz frequency
Changes to version dated June 1998:
- Added 250 MHz; changed naming conventions
Table 1. Thermal Resistance (
∅
CA) at Various Airflows
Note:
The RC5000 implements advanced power
management to substantially reduce the average power
dissipation of the device. This operation is described in
Reference
the
IDT79RV5000 RISC Microprocessor
Manual.
4
IDT RC5000
COMMERCIAL TEMPERATURE RANGE
LOGIC SYMBOL
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
System Interface
SysCmdP
ValidIn*
ValidOut*
ExtRqst*
Release*
RdRdy*
WrRdy*
64
8
9
2
ScWord (1:0)
ScTDE*
ScTOE*
ScCLR*
ScDCE*
ScDOE*
ScCWE*
Secondary Cache Interface
JTAG
Interface
Initialization
Interface
Interrupt
Interface
ScTCE*
16
ScLine (15:0)
ScMATCH
ScVALID
Clock Interface
SysClock
VccP
VssP
Vcc
Vss
34
34
RC5000
Logic
Symbol
6
Int (5:0)*
NMI*
BigEndian
ModeClock
ModeIN
VccOk
ColdReset*
Reset*
JTDI
JTDO
JTMS
JTCK
Figure 1. RC5000 Logic Symbol
5
