Control Integrated POwer
System (CIPOS™)
IKCM15H60HA
Datasheet
For Power Management Application
1
Ver. 1.2, 2014-06-01
CIPOS™ IKCM15H60HA
Table of Contents
CIPOS™ Control Integrated POwer System ........................................................................................................ 3
Features
.............................................................................................................................................................. 3
Target Applications
........................................................................................................................................... 3
Description
......................................................................................................................................................... 3
System Configuration
....................................................................................................................................... 3
Pin Configuration .................................................................................................................................................... 4
Internal Electrical Schematic ................................................................................................................................. 4
Pin Assignment ....................................................................................................................................................... 5
Pin Description
.................................................................................................................................................. 5
HIN(U,V,W) and LIN(U,V,W) (Low side and high side control pins, Pin 7 - 12) ................................................ 5
VFO (Fault-output, Pin 14) ................................................................................................................................ 6
ITRIP (Over current detection function, Pin 15) ................................................................................................ 6
VDD, VSS (Low side control supply and reference, Pin 13, 16) ....................................................................... 6
VB(U,V,W) and VS(U,V,W) (High side supplies, Pin 1 - 6) ............................................................................... 6
NW, NV, NU (Low side emitter, Pin 17 - 19) ..................................................................................................... 6
W, V, U (High side emitter and low side collector, Pin 20 - 22) ........................................................................ 6
P (Positive bus input voltage, Pin 23)................................................................................................................ 6
Absolute Maximum Ratings................................................................................................................................... 7
Module Section
.................................................................................................................................................. 7
Inverter Section..................................................................................................................................................
7
Control Section
.................................................................................................................................................. 7
Recommended Operation Conditions .................................................................................................................. 8
Static Parameters ................................................................................................................................................... 9
Dynamic Parameters ............................................................................................................................................ 10
Bootstrap Parameters .......................................................................................................................................... 10
Mechanical Characteristics and Ratings............................................................................................................ 11
Circuit of a Typical Application ........................................................................................................................... 12
Switching Times Definition .................................................................................................................................. 12
Electrical characteristic ....................................................................................................................................... 13
Package Outline .................................................................................................................................................... 14
Datasheet
2
Ver. 1.2, 2014-06-01
CIPOS™ IKCM15H60HA
CIPOS™
Control Integrated POwer System
Dual In-Line Intelligent Power Module
3Φ-bridge 600V / 15A
Features
Fully isolated Dual In-Line molded module
TrenchStop
®
IGBTs
Rugged SOI gate driver technology with stability
against transient and negative voltage
Allowable negative VS potential up to -11V for
signal transmission at VBS=15V
Integrated bootstrap functionality
Over current shutdown
Under-voltage lockout at all channels
Low side emitter pins accessible for all phase
current monitoring (open emitter)
Cross-conduction prevention
All of 6 switches turn off during protection
Lead-free terminal plating; RoHS compliant
Description
The CIPOS™ module family offers the chance for
integrating various power and control components
to increase reliability, optimize PCB size and system
costs.
It is designed to control three phase AC motors and
permanent magnet motors in variable speed drives
for applications like a washing machine. The
package concept is specially adapted to power
applications, which need good thermal conduction
and electrical isolation, but also EMI-save control
and overload protection.
TrenchStop
®
IGBTs and anti parallel diodes are
combined with an optimized SOI gate driver for
excellent electrical performance.
System Configuration
3 half bridges with TrenchStop
®
IGBTs and anti
parallel diodes
3Φ SOI gate driver
Pin-to-heasink creepage distance typ. 1.6mm
Target Applications
Washing machines
Fans
Low power motor drives
Datasheet
3
Ver. 1.2, 2014-06-01
CIPOS™ IKCM15H60HA
Pin Configuration
Bottom View
Figure 1: Pin configuration
Internal Electrical Schematic
Figure 2: Internal schematic
Datasheet
4
Ver. 1.2, 2014-06-01
CIPOS™ IKCM15H60HA
Pin Assignment
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Name
VS(U)
VB(U)
VS(V)
VB(V)
VS(W)
VB(W)
HIN(U)
HIN(V)
HIN(W)
LIN(U)
LIN(V)
LIN(W)
VDD
VFO
ITRIP
VSS
NW
NV
NU
W
V
U
P
NC
Pin Description
U-phase high side floating IC supply offset voltage
U-phase high side floating IC supply voltage
V-phase high side floating IC supply offset voltage
V-phase high side floating IC supply voltage
W-phase high side floating IC supply offset voltage
W-phase high side floating IC supply voltage
U-phase high side gate driver input
V-phase high side gate driver input
W-phase high side gate driver input
U-phase low side gate driver input
V-phase low side gate driver input
W-phase low side gate driver input
Low side control supply
Fault output
Over current shutdown input
Low side control negative supply
W-phase low side emitter
V-phase low side emitter
U-phase low side emitter
Motor W-phase output
Motor V-phase output
Motor U-phase output
Positive bus input voltage
No Connection
Pin Description
HIN(U,V,W) and LIN(U,V,W) (Low side and high
side control pins, Pin 7 - 12)
These pins are positive logic and they are
responsible for the control of the integrated IGBT.
The Schmitt-trigger input thresholds of them are
such to guarantee LSTTL and CMOS compatibility
down to 3.3V controller outputs. Pull-down resistor
of about 5k is internally provided to pre-bias inputs
during supply start-up and a zener clamp is
provided for pin protection purposes. Input Schmitt-
trigger and noise filter provide beneficial noise
rejection to short input pulses.
The noise filter suppresses control pulses which are
below the filter time
t
FILIN
. The filter acts according to
Figure 4.
5
k
Figure 3: Input pin structure
Figure 4: Input filter timing diagram
Datasheet
5
Ver. 1.2, 2014-06-01
