PCIX I/O System Clock Generator with EMI Control Features
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33.3 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• Output grouped in two banks of five clocks each
• One REF XIN clock output
• SMBus clock control interface for individual clock
disabling and SSCG control and individual back
frequency selection
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter < 250 psec (175 psec with all outputs at the
same frequency)
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pins for entire output bank enable control and
testability
• 48-pin SSOP and TSSOP packages
Table 1. Test Mode Logic Table
[1]
Input Pins
OEA
OEB
HIGH
HIGH
HIGH
HIGH
LOW
SA1
SB1
LOW
LOW
HIGH
HIGH
X
SA0
SB0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLKA
CLKB
XIN
2 * XIN
3 * XIN
4 * XIN
Three-state
REF
XIN
XIN
XIN
XIN
Three-state
Block Diagram
Pin Configuration
REF
VDD
XIN
XOUT
VSS
SA0
SA1
VSS
CLKA0
CLKA1
VDDA
CLKA2
VSS
VDDA
CLKA3
CLKA4
VSS
AGOOD#
VSS
IA0
IA1
IA2
AVDD
OEA
1
2
3
4
5
6
7
8
9
10
48
47
46
45
44
43
42
41
40
39
SDATA
SCLK
VDD
VSS
VDD
SB0
SB1
VSS
CLKB0
CLKB1
VDDB
CLKB2
VSS
VDDB
CLKB3
CLKB4
VSS
BGOOD#
AVDD
AVDD
VSS
SSCG#
VSS
OEB
AGOOD#
SSCG#
SSCG
Logic
/N
1
0
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
OEA
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
OEB
BGOOD#
REF
XIN
XOUT
0
C9530
11
12
13
14
15
16
17
18
19
20
21
22
23
24
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SDATA
SCLK
IA(0:2)
SA(0,1)
SB(0,1)
/N
I
2
C
Control
Logic
1
Note:
1. A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state
REF.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 10
www.SpectraLinear.com
C9530
Pin Description
[3]
Pin
[2]
3
4
1
24*
25*
18
31
6*, 7*
Name
XIN
XOUT
REF
OEA
OEB
AGOOD#
BGOOD#
SA(0,1)
PWR
[4]
VDDA
VDDA
VDD
VDD
VDD
VDD
VDD
VDD
I/O
I
O
O
I
I
O
O
I
Description
Crystal Buffer input pin.
Connects to a crystal, or an external clock source. Serves
as input clock TCLK, in Test mode.
Crystal Buffer output pin.
Connects to a crystal only. When a Can Oscillator is used
or in Test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin,
typically 33.33 or 25.0 MHz
Output Enable for clock bank A.
Causes the CLKA output clocks to be in a
three-state condition when driven to a logic low level.
Output Enable for clock bank B.
Causes the CLKB output clocks to be in a
three-state condition when driven to a logic low level.
When this output signal is a logic low level, it indicates that the
output clocks of the
A bank are locked to the input reference clock.
This output is latched.
When this output signal is at a logic low level, it indicates that the
output clocks of
the B bank are locked to the input reference clock.
This output is latched.
Clock Bank A selection bits.
These control the clock frequency that will be present
on the outputs of the A bank of buffers. See
Table 1
for frequency codes and selection
values.
Clock Bank B selection bits.
These control the clock frequency that will be present
on the outputs of the B bank of buffers. See
Table 1
for frequency codes and selection
values.
SMBus address selection input pins.
See
Table 3
SMBus Address table.
Enables Spread Spectrum clock modulation when at a logic low level, see
Spread
Spectrum Clocking
on page 6.
Data for the internal SMBus circuitry.
Clock for the internal SMBus circuitry.
43*, 42*
SB(0,1)
VDD
I
20*, 21*, 22*
27*
48
47
11, 14
38, 35
2, 44, 46
23, 29, 30
9, 10, 12, 15,
16
IA(0:2)
SSCG#
SDATA
SCLK
VDDA
VDDB
VDD
AVDD
VDD
VDD
VDD
VDD
–
–
–
–
I
I
I/O
I
PWR
3.3V common power supply pin for Bank A PCI clocks CLKA.
PWR
3.3V common power supply pin for Bank B PCI clocks CLKB.
PWR
Power supply for internal Core logic.
PWR
Power for internal analog circuitry.
This supply should have a separately
decoupled current source from VDD.
O
O
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
CLKA (0:4) VDDA
40, 39, 37, 34, CLKB (0:4) VDDB
33
5, 8, 13, 17,
19, 26, 28, 32,
36, 41, 45
VSS
–
PWR
Ground pins for the device.
Notes:
2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is
connected to them.
3. A bypass capacitor (0.1
μF)
should be placed as close as possible to each V
DD
pin. If these bypass capacitors are not close to the pins their high-frequency
filtering characteristic will be cancelled by the lead inductance of the trace.
4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
Rev 1.0, November 21, 2006
Page 2 of 10
C9530
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required.
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Data Byte (N–1) – 8 bits
Acknowledge from slave
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Data Protocol
The clock driver serial protocol accepts block write a opera-
tions from the controller. The bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. The C9530 does not support the Block Read
function.
The block write protocol is outlined in
Table 2.
The addresses
are listed in
Table 3.
Table 3. SMBus Address Selection Table
SMBus Address of the Device
DE
DC
DA
D8
D6
D4
D0
D2
IA0 Bit (Pin 10)
0
1
0
1
0
1
0
1
IA1 Bit (Pin 11)
0
0
1
1
0
0
1
1
IA2 Bit (Pin 12)
0
0
0
0
1
1
1
1
Serial Control Registers
Byte 0: Function Select Register
Bit
7
6
5
4
3
2
@Pup
1
0
1
0
0
0
Name
TESTEN
SSEN
SSSEL
S1
S0
Test Mode Enable.
1 = Normal operation, 0 = Test mode
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to
a 0) 0 = OFF, 1= ON
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See
Table 4
below for clarification
SB1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
SB0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
SA1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
Description
Rev 1.0, November 21, 2006
Page 3 of 10
C9530
Byte 0: Function Select Register
(continued)
Bit
1
0
@Pup
0
1
HWSEL
Name
Description
SA0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, 42, 43 and 27), 0 = SMBus
Byte 0 bits 1-4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
0
0
1
1
Table 5. Test Table
Outputs
Test Function Clock
Frequency
CLKA
XIN/6
CLKB
XIN/4
REF
XIN
Byte0, bit5
0
1
0
1
Frequency generated from XIN
Spread @ –1.0%
Spread @ –0.5%
Description
Frequency generated from second PLL
Byte 1: A Bank and REF Clock Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
REFEN
Name
Reserved
Reserved
REF Output Enable
0 = Disable, 1= Enable
CLKA4 Output Enable
0 = Disable, 1= Enable
CLKA3 Output Enable
0 = Disable, 1= Enable
CLKA2 Output Enable
0 = Disable, 1= Enable
CLKA1 Output Enable
0 = Disable, 1= Enable
CLKA0 Output Enable
0 = Disable, 1= Enable
Description
Byte 2: PCI Register
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
18
19
22
23
24
Name
Reserved
Reserved
Reserved
CLKB4 Output Enable
0 = Disable, 1= Enable
CLKB3 Output Enable
0 = Disable, 1= Enable
CLKB2 Output Enable
0 = Disable, 1= Enable
CLKB1 Output Enable
0 = Disable, 1= Enable
CLKB0 Output Enable
0 = Disable, 1= Enable
Description
Rev 1.0, November 21, 2006
Page 4 of 10
C9530
Table 6. Suggested Oscillator Crystal Parameters
Parameter
F
o
T
C
T
S
T
A
Operating Mode
C
XTAL
R
ESR
Load Capacitance
Effective Series Resistance (ESR)
Frequency
Tolerance
See
Note 5
Stability (T
A
–10 to +60C)
Note 5
Aging (first year @ 25C)
Note 5
Parallel Resonant,
Note 5
The crystal’s rated load.
Note 5
Note 6
Description
Conditions
Min
33.0
–
–
–
–
–
–
Typ.
33.33
–
–
–
–
20
40
Max.
33.5
±100
±100
5
–
–
–
pF
Ohms
Unit
MHz
PPM
PPM
PPM
Internal Crystal Oscillator
This device will operate in two input reference clock configu-
rations. In its simplest mode a 33.33-MHz fundamental cut
parallel resonant crystal is attached to the XIN and XOUT pins.
In the second mode a 33.33-MHz input reference clock is
driven in on the IN clock from an external source. In this appli-
cation the XOUT pin must be left disconnected.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the
logic state of the S0 and S1 control bits. The source of these
control signals is determined by the SMBus register Byte 0 bit
0. At initial power-up this bit is set of a logic 1 state and thus
the frequency selections are controlled by the logic levels
present on the device’s S(0,1) pins. If the application does not
use an SMBus interface then hardware frequency selection
S(0,1) must be used. If it is desired to control the output clocks
using an SMBus interface, then this bit (B0b0) must first be set
to a low state. After this is done the device will use the contents
of the internal SMBus register Bytes 0 Bits 3 and 4 to control
the output clock’s frequency.
The following formula and schematic may be used to under-
stand and calculate either the loading specification of a crystal
for a design or the additional discrete load capacitance that
must be used to provide the correct load to a known load rated
crystal
Output Clock Three-state Control
All of the clocks in Bank A (CLKA) and Bank B (CLKB) may be
placed in a three-state condition by bringing their relevant OE
pins (OEA and OEB) to a logic LOW state. This transition to
and from a state and active condition is a totally asynchronous
event and clock glitching may occur during the transitioning
states. This function is intended as a board level testing
feature. When the output clocks are being enabled and
disabled in active environments the SMBus control register
bits are the preferred mechanism to control these signals in an
orderly and predictable manner.
C
L
=
where:
(C
XINPCB
+ C
XINFTG
+ C
XINDISC
)
x
(C
XOUTPCB
) + C
XOUTFTG
) + C
XOUTDISC
)
(C
XINPCB
+ C
XINFTG
+ C
XINDISC
)
+
(C
XOUTPCB
) + C
XOUTFTG
) + C
XOUTDISC
)
C
XTAL
..................................... = The load rating of the crystal.
C
XINFTG
= The clock generators XIN pin effective device internal capacitance to ground.
C
XOUTFTG
= The clock generators XOUT pin effective device internal capacitance to ground.
C
XINPCB
= The effective capacitance to ground of the crystal to device PCB trace.
C
XOUTPCB
= The effective capacitance to ground of the crystal to device PCB trace.
C
XINDISC
= Any discrete capacitance that is placed between the XIn pin and ground.
C
XOUTDISC
= Any discrete capacitance that is placed between the XIn pin and ground.
Notes:
5. For best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these specifi-
cations.
6. Larger values may cause this device to exhibit oscillator startup problems.
