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IMTI-65698L-45

Standard SRAM, 64KX4, 45ns, CMOS, PDSO28,

器件类别:存储    存储   

厂商名称:TEMIC

厂商官网:http://www.temic.de/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
TEMIC
Reach Compliance Code
unknown
最长访问时间
45 ns
I/O 类型
COMMON
JESD-30 代码
R-PDSO-G28
JESD-609代码
e0
内存密度
262144 bit
内存集成电路类型
STANDARD SRAM
内存宽度
4
端子数量
28
字数
65536 words
字数代码
64000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
64KX4
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装等效代码
SOP28,.4
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
并行/串行
PARALLEL
电源
5 V
认证状态
Not Qualified
最大待机电流
0.00008 A
最小待机电流
2 V
最大压摆率
0.09 mA
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
文档预览
MATRA MHS
M 65698
64 K
×
4 Ultimate CMOS SRAM
Introduction
The M 65698 is a very low power CMOS static RAM
organized as 65536
×
4 bits. It is manufactured using the
MHS high performance CMOS technology named
SCMOS.
With this process, MHS is the first to bring the solution for
applications where fast computing is as mandatory as low
consumption, such as aerospace electronics, portable
instruments or embarked systems.
Utilizing an array of six transistors (6T) memory cells, the
M 65698 combines an extremely low standby
supply current (Typical value = 0.1
µA)
with a fast access
time at 40 ns. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
Extra protection against heavy ions is given by the use of
an epitaxial layer of a P substrate.
The M 67698 is 100 % processed following the test
methods of MIL STD 883 and/or ESA/SCC 9000, making
it ideally suitable for military/space applications that
demand superior levels of performance and reliability.
Features
D
Access time
commercial : 35(*), 40, 45, 55 ns
industrial and military : 40(*), 45, 55 ns
D
Very low power consumption
active : 50 mW (typ)
standby : 0.5 W (typ)
data retention : 0.4 W (typ)
D
Wide temperature range : -55 to + 125
°C
(*) Preliminary. Consult sales.
D
D
D
D
D
D
300 mils width package
TTL compatible inputs and outputs
Asynchronous
Single 5 volt supply
Equal cycle and access time
Gated inputs :
no pull-up/down
resistors are required
Interface
Block Diagram
Rev. C (12/12/94)
1
M 65698
Pin Configuration
Side Brazed 300 mils 24 pins
MATRA MHS
(*) SOIC 300 mils 28 pins
(*) Multilayer Flat Pack 28 pins
(*) Consult sales for availability
(Top View)
Pin Description
A
0
-A
15
I/O1-I/O4
V
CC
V
SS
:
:
:
:
Address inputs
Input/Output
Power
Ground
CS
W
:
:
Chip-Select
Write Enable
Truth Table
CS
H
L
L
W
X
H
L
INPUTS/
OUTPUTS
Z
DATA OUT
DATA IN
MODE
Deselect/
POWER-DOWN
Read
Write
L = low, H = high, X = H or L, Z = high impedance
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . –0.5 V to + 7.0 V
Input or Output voltage applied : . . . . . (Gnd – 0.3 V) to (Vcc + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . –65
°C
to + 150
°C
Electro static discharge voltage . . . . . . . . . . > 1250 V (MIL STD 883,
METHOD 3015)
Operating Range
OPERATING VOLTAGE
Military
Industrial
Commercial
V
CC
= 5 V
±
10 %
V
CC
= 5 V
±
10 %
V
CC
= 5 V
±
10 %
OPERATING TEMPERATURE
– 55
_C
to + 125
_C
– 40
_C
to 85
_C
0
_C
to 70
_C
DC Operating Conditions
PARAMETER
Vcc
Gnd
VIL
VIH(1)
Note :
(1)
DESCRIPTION
Supply voltage
Ground
Input low voltage
Input high voltage
MINIMUM
4.5
0.0
– 0.3
2.2
TYPICAL
5.0
0.0
0.0
MAXIMUM
5.5
0.0
0.8
Vcc + 0.3
UNIT
V
V
V
V
1. VIH max = Vcc + 0.3 V, VIL min = –0.3 V or –1.0 pulse 50 ns.
2
Rev. C (12/12/94)
MATRA MHS
Capacitance
PARAMETER
Cin
Cout
Note :
(2)
(2)
M 65698
DESCRIPTION
Input capacitance
Output capacitance
MINIMUM
TYPICAL
MAXIMUM
8
8
UNIT
pF
pF
2. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested.
DC Parameter
PARAMETER
IIX
IOZ (3)
VOL
VOH
Notes :
(4)
(4)
(3)
DESCRIPTION
Input leakage current
Output leakage current
Output low voltage
Output high voltage
MINIMUM
– 1.0
– 1.0
2.4
TYPICAL
MAXIMUM
1.0
1.0
0.4
UNIT
µA
µA
V
V
3. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
4. Vcc min, IOL = 4 mA, IOH = –1.0 mA.
Consumption for Commercial Specification
SYMBOL
ICCSB
(5)
ICCSB1
(6)
ICCOP
(7)
PARAMETER
Standby supply
current
Standby supply
current
Operating supply
current
M 65698 M 65698 M 65698 M 65698 M 65698 M 65698 M 65698 M 65698
UNIT
L-35(*) V-35(*) L - 40 V - 40 L - 45 V - 45 L - 55 V - 55
10
75
90
5
5
70
10
75
90
5
5
70
10
75
90
5
5
70
10
75
90
5
5
70
mA
µA
mA
VALUE
max
max
max
Consumption for Industrial Specification
SYMBOL
ICCSB
(5)
ICCSB1
(6)
ICCOP
(7)
PARAMETER
Standby supply
current
Standby supply
current
Operating supply
current
M 65698
L - 40(*)
10
100
90
M 65698
V - 40(*)
5
10
70
M 65698
L - 45
10
100
90
M 65698
V - 45
5
10
70
M 65698
L - 55
10
100
90
M 65698
V - 55
5
10
70
UNIT
mA
µA
mA
VALUE
max
max
max
Consumption for Military Specification
SYMBOL
ICCSB
(5)
ICCSB1
(6)
ICCOP
(7)
Notes :
5.
6.
7.
(*)
PARAMETER
Standby supply
current
Standby supply
current
Operating supply
current
M 65698
L - 40(*)
10
500
90
M 65698
V - 40(*)
5
100
70
M 65698
L - 45
10
500
90
M 65698
V - 45
5
100
70
M 65698
L - 55
10
500
90
M 65698
V - 55
5
100
70
UNIT
mA
µA
mA
VALUE
max
max
max
CS
VIH, Vin
VIH or Vin
VIL.
CS
Vcc – 0.3 V, Iout = 0 mA. Vin
Vcc – 0.3 V or Vin
0.3 V.
Vcc max, Iout = 0 mA, Vin = Gnd/Vcc. Duty cycle 100 %, f = 5 MHz, derating = 10 mA/MHz.
Preliminary. Please consult sales.
Rev. C (12/12/94)
3
M 65698
Data Retention Mode
MHS CMOS RAM’s are designed with battery backup in
mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1. Chip select (CS) must be held high during data
retention ; within Vcc to Vcc – 0.2 V.
MATRA MHS
2. CS must be kept between Vcc – 0.3 V and 70 % of
Vcc during the power up and power down transitions.
3. The RAM can begIn operation > 45 ns after Vcc
reaches the minimum operating voltage (4.5 V).
Timing
Data Retention Characteristics
PARAMETER
VCCDR
TCDR
TR
ICCDR1 (10)
DESCRIPTION
Vcc for data retention
Chip deselect to data retention
time
Operation recovery time
Data retention current
@ 2.0 V :
M-65698 V
M-65698 L
MINIMUM TYPICAL (8)
2.0
0.0
TAVAV (9)
MAXIMUM
COM
IND
8
80
MIL
80
300
UNIT
V
ns
ns
0.1
0.1
3
60
µA
µA
ICCDR2 (10)
Data retention current
@ 3.0 V :
M-65698 V
M-65698 L
0.3
0.3
4
70
9
90
90
400
µA
µA
Notes :
8. TA = 25°C.
9. TAVAV = Read cycle time.
10. CS = Vcc, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2 V.
4
Rev. C (12/12/94)
MATRA MHS
M 65698
AC Parameters
AC Conditions :
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output load : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See fig. 1a, 1b
Write Cycle : Commercial Specifications (note 12)
SYMBOL
TAVAV
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ (11)
TWLWH
TWHAX
TWHDX
TWHQX (11)
PARAMETER
Write cycle time
Address set-up time
Address valid to end of write
Data set-up time
CS low to write end
Write low to high Z
Write pulse width
Address hold to end of write
Data hold time
Write high to low Z
M 65698 M 65698
L/V - 35(*) L/V - 40
35
0
30
20
30
15
30
0
0
0
40
0
30
22
30
15
30
0
0
0
M 65698
L/V - 45
45
0
40
25
40
15
40
0
0
0
M 65698
L/V - 55
55
0
50
25
50
20
50
0
0
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALUE
min
min
min
min
min
max
min
min
min
min
Write Cycle : Industrial and Military Specification (note 12)
SYMBOL
TAVAV
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ (11)
TWLWH
TWHAX
TWHDX
TWHQX (11)
PARAMETER
Read cycle time
Address set-up time
Address valid to end of write
Data set-up time
CS low to write end
Write low to high Z
Write pulse width
Address hold to end of write
Data hold time
Write high to low Z
M 65698
L/V - 40(*)
40
0
30
22
30
15
30
0
0
0
M 65698
L/V - 45
45
0
40
25
40
15
40
0
0
0
M 65698
L/V - 55
55
0
50
25
50
20
50
0
0
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALUE
min
min
min
min
min
min
min
min
min
min
Notes :
11. Specified with C
L
= 5 pF (see figure 1b). Guaranteed. Not tested.
(*) Preliminary. Consult sales.
Rev. C (12/12/94)
5
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