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INA-31063-TR2

Wide Band Low Power Amplifier, 0MHz Min, 2500MHz Max, SOT-363, 6

器件类别:无线/射频/通信    射频和微波   

厂商名称:Hewlett Packard Co

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器件参数
参数名称
属性值
厂商名称
Hewlett Packard Co
Reach Compliance Code
unknown
Is Samacsys
N
特性阻抗
50 Ω
最大输入功率 (CW)
7 dBm
最大工作频率
2500 MHz
最小工作频率
射频/微波设备类型
WIDE BAND LOW POWER
最大电压驻波比
3.5
Base Number Matches
1
文档预览
DC – 2.5 GHz 3 V, High Isolation
Silicon RFIC Amplifier
Technical Data
INA-31063
Features
• High Reverse Isolation
-40 dB at 1.9 GHz
• Single +3V Supply
• 15 dB |S
21
|
2
at 1.9 GHz
• 200
Output Impedance
• Ultra-Miniature Package
• Unconditionally Stable
Surface Mount SOT-363
(SC-70) Package
Description
Hewlett-Packard’s INA-31063 is a
Silicon RFIC amplifier that has
excellent gain and isolation for
applications to 2.5 GHz. Packaged
in an ultra-miniature SOT-363
package, it requires half the board
space of a SOT-143 package.
The INA-31063 uses a unique
circuit topology that provides
broadband gain and 50
input
and 200
output impedance.
With more than 35 dB of isolation
to 2.5 GHz makes it an excellent
candidate for LO buffer
applications.
The INA-31063 is fabricated using
HP’s 30 GHz f
MAX
ISOSAT
TM
Silicon bipolar process which
uses nitride self-alignment,
submicrometer lithography,
trench isolation, ion implantation,
and polyimide intermetal dielec-
tric and scratch protection to
achieve superior performance,
uniformity, and reliability.
Applications
• LO Buffer and Amplifier for
Cellular, Cordless, Special
Mobile Radio, PCS, ISM,
Wireless LAN, DBS, TVRO,
and TV Tuner
Pin Connections and
Package Marking
GND 2 1
6 OUTPUT
& V
d
5 GND 1
4 V
d
31
GND 1 2
INPUT 3
Note:
Package marking provides
orientation and identification.
Simplified Schematic
V
d
Output & V
d
Input
Gnd1
Gnd2
2
Absolute Maximum Ratings
Symbol
V
d
P
in
T
j
T
STG
Parameter
Device Voltage,
output to ground
CW RF Input Power
Junction Temperature
Storage Temperature
Units
V
dBm
°C
°C
Absolute
Maximum
[1]
6.0
+7.0
150
-65 to 150
Thermal Resistance
[2]
:
θ
jc
= 170°C/W
Notes:
1. Operation of this device above any one
of these limits may cause permanent
damage.
2. T
C
= 25°C (T
C
is defined to be the
temperature at the package pins where
contact is made to the circuit board)
INA-31063 Electrical Specifications
, T
C
= 25°C, Z
O
= 50
Ω,V
d
= 3 V
Symbol
|S
21
|
2
Parameters and Test Conditions
Gain in 50
system
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Noise Figure
f = 1.9 GHz
Output Power at 1 dB Gain Compression
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Output Third Order Intercept Point
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Input VSWR
f = 0.1 – 2.4 GHz
Output VSWR
f = 0.1 – 2.4 GHz
Device Current
Units Min.
dB
13.0
[3]
dB
dBm
Typ. Max. Std.
Dev.
[4]
14.0
15.1
0.44
15.0
6.1
0.25
-1.8
-2.1
-3.5
9.1
8.5
6.8
1.35:1
3.5:1
11.0 13.5
[3]
0.47
NF
50
P
1dB
IP
3
dBm
VSWR
in
VSWR
out
Ι
d
mA
Notes:
3. Guaranteed specifications are 100% tested in production.
4. Standard deviation number is based on measurement of a large number of parts from three non-consecutive wafer lots
during the initial characterization of this product, and is intended to be used as an estimate for distribution of the
typical specification.
3
INA-31063 Typical Performance,
T
C
= 25°C, Z
O
= 50
Ω,
V
d
= 3 V
20
7.5
7
NOISE FIGURE (dB)
15
GAIN (dB)
6.5
6
5.5
5
4.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
2.7 V
3.0 V
3.3 V
P
1 dB
(dBm)
4
2
0
-2
-4
-6
-8
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
2.7 V
3.0 V
3.3 V
10
5
2.7 V
3.0 V
3.3 V
0
0.5
0
FREQUENCY (GHz)
Figure 1. Gain vs. Frequency and
Voltage measured in a 50
system.
Figure 2. Noise Figure vs. Frequency
and Voltage.
Figure 3. Output Power for 1 dB Gain
Compression vs. Frequency and
Voltage.
4
20
8
-40°C
+25°C
+85°C
2
0
-2
-4
-6
15
NOISE FIGURE
(dB)
7
P
1 dB
(dBm)
-40°C
+25°C
+85°C
GAIN (dB)
10
6
5
-40°C
+25°C
+85°C
0
0.5
1.0
1.5
2.0
2.5
5
0
4
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
-8
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 4. Gain vs. Frequency and
Temperature measured in a 50
system.
Figure 5. Noise Figure vs. Frequency
and Temperature.
Figure 6. Output Power for 1 dB Gain
Compression vs. Frequency and
Temperature.
4
25
-40°C
+25°C
+85°C
14
12
10
20
3
15
I
d
(mA)
VSWR
2
IP
3
(dBm)
8
6
10
1
VSWR in
VSWR out
0
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
5
4
2
0
1
2
V
d
(V)
3
4
5
0
-40°C
+25°C
+85°C
0.5
1.0
1.5
2.0
2.5
0
FREQUENCY (GHz)
Figure 7. Input and Output VSWR vs.
Frequency.
Figure 8. Supply Current vs. Voltage
and Temperature.
Figure 9. Third Order Intercept
Point, IP
3
vs. Frequency and
Temperature.
4
INA-31063 Typical Scattering Parameters
[5]
, T
C
= 25°C, Z
O
= 50
Ω,V
d
= 3.0 V
Freq.
GHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
Note:
5. Reference plane per Figure 19 in Applications Information section.
S
11
Mag
0.14
0.15
0.14
0.15
0.15
0.14
0.14
0.15
0.14
0.14
0.14
0.13
0.13
0.13
0.13
0.12
0.12
0.12
0.12
0.11
0.10
0.08
0.07
0.05
0.04
0.04
0.05
0.06
0.08
0.10
0.13
0.15
0.17
0.19
0.21
0.22
0.24
0.25
0.25
0.26
0.27
0.27
0.28
0.29
0.29
0.30
0.31
0.32
0.33
0.33
Ang
171
167
164
163
152
152
151
147
143
138
137
136
132
129
125
128
130
130
130
128
129
130
134
144
166
-176
-159
-151
-149
-150
-152
-153
-155
-158
-160
-161
-163
-165
-167
-169
-172
-175
-178
180
177
174
171
169
166
164
dB
13.6
13.7
13.7
13.7
13.8
13.8
13.9
14.0
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.6
14.8
14.9
15.1
15.2
15.3
15.3
15.1
15.0
14.8
14.5
14.1
13.7
13.3
12.8
12.3
11.8
11.3
10.7
10.1
9.6
9.1
8.5
8.0
7.5
7.0
6.5
6.1
5.6
5.1
4.7
4.3
3.8
3.4
3.0
S
21
Mag
4.81
4.84
4.83
4.86
4.88
4.88
4.93
4.99
5.04
5.06
5.12
5.20
5.26
5.33
5.34
5.36
5.49
5.57
5.69
5.77
5.83
5.79
5.71
5.63
5.50
5.29
5.06
4.84
4.62
4.36
4.11
3.89
3.65
3.42
3.20
3.02
2.84
2.66
2.51
2.37
2.24
2.12
2.01
1.90
1.81
1.72
1.63
1.55
1.48
1.41
Ang
-5
-11
-15
-20
-26
-30
-35
-40
-45
-51
-56
-61
-67
-73
-80
-85
-91
-97
-104
-111
-119
-127
-135
-143
-152
-160
-167
-174
178
172
165
159
153
147
142
137
132
128
124
120
116
112
109
105
102
98
95
92
89
87
dB
-32.5
-37.1
-36.0
-37.6
-39.8
-37.1
-38.6
-41.3
-45.5
-45.2
-44.1
-45.3
-47.3
-46.8
-41.9
-41.5
-44.3
-45.0
-46.4
-45.8
-44.7
-43.4
-42.4
-41.7
-41.8
-42.2
-43.2
-43.1
-43.3
-44.2
-44.0
-43.0
-42.0
-42.2
-41.3
-38.9
-38.0
-37.3
-35.5
-34.2
-33.2
-32.4
-31.3
-30.5
-29.7
-28.9
-28.3
-27.7
-27.0
-26.2
S
12
Mag
0.024
0.014
0.016
0.013
0.010
0.014
0.012
0.009
0.005
0.005
0.006
0.005
0.004
0.005
0.008
0.008
0.006
0.006
0.005
0.005
0.006
0.007
0.008
0.008
0.008
0.008
0.007
0.007
0.007
0.006
0.006
0.007
0.008
0.008
0.009
0.011
0.013
0.014
0.017
0.019
0.022
0.024
0.027
0.030
0.033
0.036
0.039
0.041
0.045
0.049
Ang
10
11
-3
-39
-6
-18
-35
-46
-35
-4
-6
-16
20
40
58
30
27
31
53
61
74
78
79
76
74
76
77
85
86
96
105
115
118
125
139
143
144
151
155
153
153
154
154
154
153
152
151
151
151
150
S
22
Mag
Ang
0.49
0.52
0.51
0.54
0.53
0.51
0.53
0.55
0.56
0.55
0.54
0.55
0.55
0.55
0.53
0.49
0.50
0.50
0.51
0.52
0.53
0.52
0.50
0.49
0.49
0.47
0.44
0.40
0.39
0.36
0.34
0.32
0.30
0.29
0.27
0.25
0.24
0.23
0.21
0.21
0.20
0.20
0.19
0.19
0.19
0.19
0.19
0.19
0.19
0.19
-3
-4
-4
-3
-5
-5
-5
-8
-11
-14
-17
-19
-24
-28
-35
-36
-37
-40
-44
-48
-54
-62
-68
-73
-80
-87
-93
-97
-100
-105
-108
-109
-111
-113
-115
-114
-114
-115
-113
-111
-109
-108
-105
-103
-101
-99
-98
-97
-95
-93
K
Factor
3.45
5.37
4.79
5.60
7.31
5.38
6.02
7.66
13.54
13.71
11.32
13.20
16.34
12.92
8.32
8.84
11.23
11.18
12.80
12.59
10.20
8.94
8.22
8.42
8.64
9.24
11.43
12.34
13.10
16.46
17.71
16.22
15.17
16.23
15.49
13.50
12.09
12.00
10.55
9.98
9.10
8.83
8.26
7.82
7.47
7.17
6.94
6.89
6.54
6.30
5
INA-31063 Applications
Information
Introduction
The INA-31063 is a +3 volt silicon
RFIC amplifier that is designed
with a two stage internal network
to provide a broadband gain and
50
input and 200
output
impedance. With a P
-l dB
com-
pressed output power of -3 dBm
and high isolation of 40 dB, the
INA-31063 is well suited for LO
buffer amplifier applications in
mobile communication systems.
The 200
output impedance of
the amplifier allows easy connec-
tions to additional RFICs and
some filters.
In addition to use in buffer
applications in the cellular
market, the INA-31063 will find
many applications in battery
operated wireless communication
systems.
Operating Details
The INA-31063 is a voltage biased
device that operates from a
+3 volt power supply with a
typical current drain of 11 mA.
All bias regulation circuitry is
integrated into the RFIC.
Figure 10 shows a typical imple-
mentation of the INA-31063. The
supply voltage for the INA-31063
must be applied to two terminals,
the V
d
pin and the RF Output pin.
Gnd2
C
out
Gnd1
RF
Output
RFC
V
d
C
block
C
bypass
The V
d
connection to the ampli-
fier is RF bypassed by placing a
capacitor to ground near the V
d
pin of the amplifier package. The
power supply connection to the
RF Output pin is achieved by
means of a RF choke (inductor).
The value of the RF choke must
be large relative to 50
in order
to prevent loading of the RF
Output. The supply voltage end of
the RF choke is bypassed to
ground with a capacitor. If the
physical layout permits, this can
be the same bypass capacitor that
is used at the V
d
terminal of the
amplifier. Blocking capacitors are
normally placed in series with the
RF Input and the RF Output to
isolate the DC voltages on these
pins from circuits adjacent to the
amplifier. The values for the
blocking and bypass capacitors
are selected to provide a reac-
tance at the lowest frequency of
operation that is small relative to
50
Ω.
Since the gain of the
INA-31063 extends down to DC,
the frequency response of the
amplifier is limited only by the
values of the capacitors and
choke.
the circuit board). The circuit
board material is 0.031-inch thick
FR4. Plated through holes (vias)
are used to bring the ground to
the top side of the circuit where
needed. The performance of
INA-31063 is sensitive to ground
path inductance. The two-stage
design creates the possibility of a
feedback loop being formed
through the ground returns of the
stages, Gnd 1 and Gnd 2.
Gnd 1
Gnd 2
VIA
Figure 12. INA-31063 Potential
Ground Loop.
Gnd 1
VIA
Gnd 2
VIA
RF Layout
An example for the RF layout for
the INA-31063 is shown in
Figure 11.
Gnd 1
50
Gnd 2
50
RF Output
and Vd
Gnd 1
Figure 11. RF Layout
Figure 13. INA-31063 Suggested
Layout.
At least one ground via should be
placed adjacent to each ground
pin to assure good RF grounding.
Multiple vias are used to reduce
the inductance of the path to
ground and should be placed as
close to the package terminals as
practical.
The effects of the potential
ground loop shown in Figure 12
may be observed as a “peaking” in
the gain versus frequency
response, an increase in input
VSWR, or even as return gain at
the input of the INA-31063.
31
Gnd1
RF
Input
Figure 10. Basic Amplifier
Application.
This example uses a
microstripline design (solid
groundplane on the backside of
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