About The Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
Contents
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core...
1-1
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features....................1-3
Low Latency 40-100GbE IP Core Device Family and Speed Grade Support...................................... 1-4
Device Family Support.................................................................................................................... 1-5
Low Latency 40-100GbE IP Core Device Speed Grade Support............................................... 1-5
IP Core Verification..................................................................................................................................... 1-6
Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices...................................... 2-2
Licensing IP Cores....................................................................................................................................... 2-3
OpenCore Plus IP Evaluation.........................................................................................................2-3
Specifying the Low Latency 40-100GbE IP Core Parameters and Options......................................... 2-4
IP Core Parameters...................................................................................................................................... 2-5
Files Generated for Stratix V Variations................................................................................................. 2-14
Files Generated for Arria 10 Variations.................................................................................................. 2-15
Integrating Your IP Core in Your Design................................................................................................2-18
External Transceiver Reconfiguration Controller Required in Stratix V Designs................ 2-19
Transceiver PLL Required in Arria 10 Designs..........................................................................2-20
External Time-of-Day Module for Variations with 1588 PTP Feature...................................2-22
Clock Requirements for 40GBASE-KR4 Variations..................................................................2-23
External TX MAC PLL..................................................................................................................2-23
Placement Settings for the Low Latency 40-100GbE IP Core..................................................2-23
Low Latency 40-100GbE IP Core Testbenches...................................................................................... 2-23
Low Latency 40-100GbE IP Core Testbench Overview............................................................2-24
Understanding the Testbench Behavior......................................................................................2-27
Simulating the Low Latency 40-100GbE IP Core With the Testbenches........................................... 2-28
Generating the Low Latency 40-100GbE Testbench.................................................................2-29
Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches..........2-30
Simulating with the Modelsim Simulator...................................................................................2-30
Simulating with the NCSim Simulator........................................................................................2-31
Simulating with the VCS Simulator.............................................................................................2-31
Testbench Output Example: Low Latency 40-100GbE IP Core...............................................2-31
Altera Corporation
About The Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
TOC-3
Compiling the Full Design and Programming the FPGA.................................................................... 2-32
Initializing the IP Core.............................................................................................................................. 2-32
How to Contact Altera..............................................................................................................................C-11
Low Latency 40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller
(MAC) and PHY MegaCore
®
functions offer the lowest round-trip latency and smallest size to implement
the
IEEE 802.3ba 40G and 100G Ethernet Standard
with an option to support the
IEEE 802.3ap-2007
Backplane Ethernet Standard.
Note:
This user guide documents the 16.0 version of the Altera Low Latency 40- and 100-Gbps Ethernet
MAC and PHY IP core that targets a Stratix
®
V device or an Arria
®
10 device. For the 16.1 release
and beyond, two IP core user guides are available to document the Low Latency 40-Gbps Ethernet
IP core and the Low Latency 100-Gbps Ethernet IP core separately. These two user guides
document the variations that target an Arria 10 device. As of 2017.12.28, the 16.0 version of the
Stratix V Low Latency 40-100GbE IP core is the most recent Stratix V Low Latency 40-100GbE IP
core available in the Self-Service Licensing Center and this user guide provides its most current
documentation.
The version of this product that supports Arria 10 devices is included in the Altera MegaCore IP Library
and available from the Quartus
®
Prime IP Catalog.
Note:
The full product name, Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore
Function, is shortened to Low Latency (LL) 40-100GbE IP core in this document. In addition,
although multiple variations are available from the parameter editor, this document refers to this
product as a single IP core, because all variations are configurable from the same parameter editor.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
微控制器 MCU
