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External Memory Interface Handbook
Volume 3: Reference Material
November 2012
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15–2
Chapter 15: Introduction to ALTMEMPHY IP
Release Information
The example top-level file is a fully-functional design that you can simulate,
synthesize, and use in hardware. The example driver is a self-test module that issues
read and write commands to the controller and checks the read data to produce the
pass or fail, and test complete signals.
The ALTMEMPHY megafunction creates the datapath between the memory device
and the memory controller. The megafunction is available as a stand-alone product or
can be used in conjunction with the Altera high-performance memory controller.
When using the ALTMEMPHY megafunction as a stand-alone product, use with
either custom or third-party controllers.
1
For new designs, Altera recommends using a UniPHY-based external memory
interface, such as the DDR2 and DDR3 SDRAM controllers with UniPHY, QDR II and
QDR II+ SRAM controllers with UniPHY, or RLDRAM II controller with UniPHY.
Release Information
Table 15–1
provides information about this release of the DDR3 SDRAM Controller
with ALTMEMPHY IP.
Table 15–1. Release Information
Item
Version
Release Date
Ordering Codes
11.1
November 2011
IP-SDRAM/HPDDR (DDR SDRAM HPC)
IP-SDRAM/HPDDR2 (DDR2 SDRAM HPC)
IP-HPMCII (HPC II)
00BE (DDR SDRAM)
Product IDs
00BF (DDR2 SDRAM)
00C2 (DDR3 SDRAM)
00CO (ALTMEMPHY Megafunction)
Vendor ID
6AF7
Description
Altera verifies that the current version of the Quartus
®
II software compiles the
previous version of each MegaCore function. The
MegaCore IP Library Release Notes
and Errata
report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release. For information
about issues on the DDR, DDR2, or DDR3 SDRAM high-performance controller and
the ALTMEMPHY megafunction in a particular Quartus II version, refer to the
Quartus II Software Release Notes.
External Memory Interface Handbook
Volume 3: Reference Material
November 2012 Altera Corporation
Chapter 15: Introduction to ALTMEMPHY IP
Device Family Support
15–3
Device Family Support
Table 15–2
defines the device support levels for Altera IP cores.
Table 15–2. Altera IP Core Device Support Levels
FPGA Device Families
Preliminary support—The
IP core is verified with
preliminary timing models for this device family. The IP core
meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be
used in production designs with caution.
Final support—The
IP core is verified with final timing
models for this device family. The IP core meets all
functional and timing requirements for the device family and
can be used in production designs.
HardCopy Device Families
HardCopy Companion—The
IP core is verified with
preliminary timing models for the HardCopy companion
device. The IP core meets all functional requirements, but
might still be undergoing timing analysis for the HardCopy
device family. It can be used in production designs with
caution.
HardCopy Compilation—The
IP core is verified with final
timing models for the HardCopy device family. The IP core
meets all functional and timing requirements for the device
family and can be used in production designs.
Table 15–3
shows the level of support offered by the DDR, DDR2, and DDR3 SDRAM
Controllers with ALTMEMPHY IP for Altera device families.
Table 15–3. Device Family Support
Protocol
Device Family
DDR and DDR2
Arria
®
GX
Arria II GX
Cyclone
®
III
Cyclone III LS
Cyclone IV E
Cyclone IV GX
HardCopy II
Stratix
®
II
Stratix II GX
Other device families
Final
Final
Final
Final
Final
Final
Refer to the
What’s New in Altera
IP
page of the Altera website.
Final
Final
No support
No support
Final
No support
No support
No support
No support
No support
No support
No support
No support
DDR3
November 2012
Altera Corporation
External Memory Interface Handbook
Volume 3: Reference Material
15–4
Chapter 15: Introduction to ALTMEMPHY IP
Features
Features
ALTMEMPHY Megafunction
Table 15–4
summarizes key feature support for the ALTMEMPHY megafunction.
Table 15–4. ALTMEMPHY Megafunction Feature Support
Feature
Support for the Altera PHY Interface (AFI) on all supported
devices.
Automated initial calibration eliminating complicated read data
timing calculations.
Voltage and temperature (VT) tracking that guarantees maximum
stable performance for DDR, DDR2, and DDR3 SDRAM
interfaces.
Self-contained datapath that makes connection to an Altera
controller or a third-party controller independent of the critical
timing paths.
Full-rate interface
Half-rate interface
Easy-to-use parameter editor
DDR and DDR2
v
v
v
DDR3
v
v
v
v
v
v
v
v
—
v
v
In addition, the ALTMEMPHY megafunction supports DDR3 SDRAM components
without leveling:
■
The ALTMEMPHY megafunction supports DDR3 SDRAM components without
leveling for Arria II GX devices using T-topology for clock, address, and command
bus:
■
Supports multiple chip selects.
■
■
The DDR3 SDRAM PHY without leveling f
MAX
is 400 MHz for single chip selects.
No support for data-mask (DM) pins for ×4 DDR3 SDRAM DIMMs or
components, so select
No
for
Drive DM pins from FPGA
when using ×4 devices.
The ALTMEMPHY megafunction supports half-rate DDR3 SDRAM interfaces
only.
■
High-Performance Controller II
Table 15–5
summarizes key feature support for the DDR, DDR2, and DDR3 SDRAM
HPC II.
Table 15–5. Feature Support (Part 1 of 2)
Feature
Half-rate controller
Support for AFI ALTMEMPHY
Support for Avalon
®
Memory Mapped (Avalon-MM) local
interface
DDR and DDR2
v
v
v
DDR3
v
v
v
External Memory Interface Handbook
Volume 3: Reference Material
November 2012 Altera Corporation
Chapter 15: Introduction to ALTMEMPHY IP
Features
15–5
Table 15–5. Feature Support (Part 2 of 2)
Feature
Configurable command look-ahead bank management with
in-order reads and writes
Additive latency
Support for arbitrary Avalon burst length
Built-in flexible memory burst adapter
Configurable Local-to-Memory address mappings
Optional run-time configuration of size and mode register
settings, and memory timing
Partial array self-refresh (PASR)
Support for industry-standard DDR3 SDRAM devices
Optional support for self-refresh command
Optional support for user-controlled power-down command
Optional support for automatic power-down command with
programmable time-out
Optional support for auto-precharge read and auto-precharge
write commands
Optional support for user-controller refresh
Optional multiple controller clock sharing in SOPC Builder Flow
Integrated error correction coding (ECC) function 72-bit
Integrated ECC function, 16, 24, and 40-bit
Support for partial-word write with optional automatic error
correction
SOPC Builder ready
Support for OpenCore Plus evaluation
IP functional simulation models for use in Altera-supported VHDL
and Verilog HDL simulator
Notes to
Table 15–5:
(1) HPC II supports additive latency values greater or equal to t
RCD
-1, in clock cycle unit (t
CK
).
(2) This feature is not supported with DDR3 SDRAM with leveling
