IP175A LF
Preliminary Data Sheet
5 Port 10/100 Ethernet Integrated Switch
Features
5 port 10/100 Ethernet switch with built in
transceivers and memory
Build in SSRAM for frame buffer
Built in storage of 1K MAC address
Support flow control
– Support IEEE802.3x for flow control for full
duplex mode operation
– Support backpressure for flow control for
half duplex mode operation
5 port switching fabric
– Support two-level hashing algorithm to
solve MAC address collision
– Support MAC address aging
– Store and forward mode
– Broadcast storm protection
– Full line speed capability of 148800 (14880)
packets/sec for 100M (10M)
– Support 1536 byte data transfer for VLAN
packet traffic
– Port base VLAN
– Port base CoS configuration
Integrate 5 ports transceiver
– Each port can be auto negotiable or forced
10M/100M, full/half duplex
– Each port can be configured as 100BaseFX
– Automatic MDI/MDI-X configuration
Support two MII, one SMI and extended MII
registers for router application
Built in regulator for 3.3v to 2.15v
LED status of Link, activity, Full/half duplex,
speed, and power on diagnostic function
Initial parameter setting by pin or EEPROM
(24LC01) configuration
Utilize single clock source (25Mhz)
0.25u technology
Support Lead Free package (Please refer to
the Order Information)
General Description
IP175A LF is a low cost 10/100 Ethernet single
chip switch. It integrates a 5-port switch controller,
SSRAM, and 5 10/100 Ethernet transceivers.
Each of the transceivers complies with the
IEEE802.3,
IEEE802.3u,
and
IEEE802.3x
specifications. The transceivers are designed in
DSP approach with 0.25um technology; they have
high noise immunity and robust performance.
IP175A LF operates in store and forward mode. It
supports flow control, auto MDI/MDI-X, CoS, port
base VLAN, and LED functions, etc. Each port can
be configured to auto-negotiation or forced
10M/100M, full/half duplex, and it is also able to
configure to 100BaseFX transmission mode.
Using an EEPROM or pull up/down resistors on
specified pins can configure the desired options.
IP175A LF does not support “forced 10M half
mode”.
IP175A LF supports two MII ports for router
application, which supports 4 LAN ports and one
WAN port. MII0 is for LAN traffic and MII1 is for
WAN traffic and no external PHY is needed. Both
MII can work in PHY mode and interface to the
external MAC in this application. The external
MAC can monitor or configure IP175A LF by
accessing MII registers through SMI.
MII0 also can be configured to be MAC mode. It is
used to interface an external PHY to work as a
4+1 switch.
1/60
Copyright © 2004, IC Plus Corp.
February 20, 2006
IP175A LF-DS-R08
IP175A LF
Preliminary Data Sheet
Table Of Contents
Features ......................................................................................................................1
General Description .....................................................................................................1
Table Of Contents ........................................................................................................2
Revision History...........................................................................................................3
1 Applications ...........................................................................................................4
Applications
(continued)
.................................................................................................5
Applications
(continued)
.................................................................................................6
2 Pin Diagram...........................................................................................................7
3 Pin Descriptions.....................................................................................................8
Pin Descriptions
(continued)
...........................................................................................9
Pin Descriptions
(continued)
.........................................................................................10
Pin Descriptions
(continued)
.........................................................................................11
Pin Descriptions
(continued)
.........................................................................................12
Pin Descriptions
(continued)
.........................................................................................13
Pin Descriptions
(continued)
.........................................................................................14
Pin Descriptions
(continued)
.........................................................................................15
Pin Descriptions
(continued)
.........................................................................................17
Pin Descriptions
(continued)
.........................................................................................18
4 Functional Description .........................................................................................19
5-port switch application .....................................................................................................19
Router application...............................................................................................................20
MII0 MAC mode..................................................................................................................21
MII, SMI and MII register ....................................................................................................22
Fiber port configuration.......................................................................................................25
CoS.....................................................................................................................................26
VLAN ..................................................................................................................................27
4.7.1
Port base VLAN..................................................................................................... 27
4.7.2
Tag / un-tag............................................................................................................ 27
4.8
Initial value set by LED pins ...............................................................................................28
4.9
Built in regulator..................................................................................................................29
4.10 Extended MII registers........................................................................................................30
4.11
EEPROM register ...............................................................................................................37
4.12 The basic MII registers .......................................................................................................48
4.13 LED Blink Timming .............................................................................................................52
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5
Electrical Characteristics .....................................................................................53
5.1
5.2
5.3
Absolute Maximum Rating..................................................................................................53
DC Characteristic ...............................................................................................................53
AC Timing ...........................................................................................................................54
5.3.1
Reset Timing.......................................................................................................... 54
5.3.2
MII0 PHY Mode Timing.......................................................................................... 54
5.3.3
MII1 PHY Mode Timing.......................................................................................... 56
5.3.4
MII0 MAC Mode Timing ......................................................................................... 57
5.3.5
SMI Timing............................................................................................................. 58
5.3.6
EEPROM Timing ................................................................................................... 59
6
7
Order Information.................................................................................................59
Package Detail.....................................................................................................60
2/60
Copyright © 2004, IC Plus Corp.
February 20, 2006
IP175A LF-DS-R08
IP175A LF
Preliminary Data Sheet
Revision History
Revision #
Change Description
IP175A LF-DS-R01 Initial release.
IP175A LF-DS-R02 1. Update pin description of REG_OUT on page 14.
2. Add VCC_IO limitation to the operation condition on page 61.
3. Add VCC_IO_1, VCC_IO_2, VCC pin description on page 18
IP175A LF-DS-R03 Update pin description of Reg_out page 14.
IP175A LF-DS-R04 Remove MII register 16H.
IP175A LF-DS-R05 Remove VLAN from MII Register.
IP175A LF-DS-R06 1. ADD AC Timing
2. Change minimum VCC from 2.1v to 2.0v on page 14 & 50
IP175A LF-DS-R07 Add the order information for lead free package.
IP175A LF-DS-R08 ADD LED Blink Timing Table on page 52.
3/60
Copyright © 2004, IC Plus Corp.
February 20, 2006
IP175A LF-DS-R08
IP175A LF
Preliminary Data Sheet
1
Applications
Application 1:
IP175A LF
5x
Transformer
or
Fiber MAU
5 port Ethernet switch
Application 2:
MII0
IP175A LF
MII1
MAC2
Application 3:
MAC1
CPU
IP175A LF
MII0
4x
Transformer
or
Fiber MAU
1x
Transformer
ADSL
or
Cable
Modem
4x
Transformer
or
Fiber MAU
PHY
4 LAN port + one WAN port (Router)
4 TP ports + one external PHY
4/60
Copyright © 2004, IC Plus Corp.
February 20, 2006
IP175A LF-DS-R08
IP175A LF
Preliminary Data Sheet
Applications
(continued)
Application 1: 5 TP port switch
Switch
IP175A LF
5 port
switch controller
PHY
0
PHY
1
PHY
2
PHY
3
PHY
4
Use 5 builtin PHY.
MII0 and MII1 ports are not
used.
5 TP port
Application 1: 5 FX port switch
Switch
IP175A LF
Fiber
MAU
0
Fiber
MAU
1
Fiber
MAU
2
Fiber
MAU
3
Fiber
MAU
4
Use 5 external fiber MAU.
MII0 and MII1 ports are not
used.
5 FX port
5/60
Copyright © 2004, IC Plus Corp.
February 20, 2006
IP175A LF-DS-R08
