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ipModule
TM
Software
Customer Application
HTTP/SMTP/TFTP
TCP/UDP
IP/ICMP
Network Access Layer
PHY Firmware
Choices for
Communication:
IP2022/IP2012
8/16-Bit
Parallel
Slave Port
Internet
Processor
CPU
64-Kbyte
Flash
Memory
ipOS Operating System
16-Kbyte
Inst./Data
RAM
4-Kbyte
Data
RAM
External
Memory
Interface
General
Purpose
I/O Ports
Choices for
Communication:
ISA (802.11b)
Mini-PCI/Cardbus
(802.11g/802.11a)
I2C
General-Purpose I/O
10Base-T Ethernet
(MAC/PHY on chip)
USB 1.1 (SIE on chip)
GPSI
SPI
UART/Modem
Host Bus
10Base-T Ethernet
(MAC/PHY on chip)
USB 1.1 (SIE on chip)
GPSI
SPI
UART/Modem
High-Speed
Serial Unit 1
(SERDES)
5
Timers
PLL
Clock
Multiplier
8-Input
10-Bit
A/DC
ISP/ISD
Interface
High-Speed
Serial Unit 2
(SERDES)
515-063b.eps
Not available on IP2012
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IP2012 / IP2022 Data Sheet
1
1.1
Additional Features. . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.1
CPU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.2
Serializer/Deserializers
. . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.3
Low-Power Support
. . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.4
Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.5
Instruction Set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.6
Other Supported Functions
. . . . . . . . . . . . . . . . . . . . . . .5
1.2.7
Programming and Debugging Support
. . . . . . . . . . . . . . .5
6
2.0 Pin Definitions
2.1
PQFP (Plastic Quad Flat Package) for IP2022. . . . . .6
2.2
PQFP (Plastic Quad Flat Package) for IP2012. . . . . .7
2.3
µBGA (Micro Ball Grid Array) IP2022-120 Only . . . . .8
2.4
Signal Descriptions — IP2022 . . . . . . . . . . . . . . . . . .9
2.5
Signal Descriptions — IP2012 . . . . . . . . . . . . . . . . .12
15
3.0 System Architecture
3.1
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3.1
Loading the Program RAM
. . . . . . . . . . . . . . . . . . . . . .19
3.3.2
Program Counter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4
Low Power Support . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4.1
Clock Stop Mode (SLEEP)
. . . . . . . . . . . . . . . . . . . . . .21
3.4.2
Wakeup
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5
Speed Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.6
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.7
Interrupt Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.7.1
Interrupt Processing
. . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.7.2
Global Interrupt Enable Bit
. . . . . . . . . . . . . . . . . . . . . .25
3.7.3
Interrupt Latency
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.7.4
Return From Interrupt
. . . . . . . . . . . . . . . . . . . . . . . . . .25
3.7.5
Disabled Interrupt Resources
. . . . . . . . . . . . . . . . . . . .26
3.8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.8.1
Brown-Out Detector
. . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.8.2
Reset and Interrupt Vectors
. . . . . . . . . . . . . . . . . . . . . .28
3.8.3
Register States Following Reset
. . . . . . . . . . . . . . . . . .28
3.9
Clock Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.9.1
External Clock Connections
. . . . . . . . . . . . . . . . . . . . .30
3.10
Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . .31
3.10.1
FUSE0 Register (not run-time programmable)
. . . . . . . . .32
3.10.2
FUSE1 Register (not run-time programmable)
. . . . . . . . .33
3.10.3
TRIM0 Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
35
4.0 Instruction Set Architecture
4.1
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1.1
Pointer Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1.2
Direct Addressing Mode
. . . . . . . . . . . . . . . . . . . . . . . .36
4.1.3
Indirect Addressing Mode
. . . . . . . . . . . . . . . . . . . . . . .36
4.1.4
Indirect-with-Offset Addressing Mode
. . . . . . . . . . . . . . .37
4.2
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.2.1
Instruction Formats
. . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.2.2
Instruction Types
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.3
Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4
Subroutine Call/Return Stack . . . . . . . . . . . . . . . . . .41
4.5
Key to Abbreviations and Symbols . . . . . . . . . . . . . .42
4.6
Instruction Set Summary Tables. . . . . . . . . . . . . . . .42
4.7
Self-Programming and Read Instructions. . . . . . . . .47
4.7.1
Flash Timing Control
. . . . . . . . . . . . . . . . . . . . . . . . . .48
4.7.2
Interrupts During Flash Operations
. . . . . . . . . . . . . . . . .48
49
5.0 Peripherals
5.1
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.1.1
Port B Interrupts
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.1.2
Reading and Writing the Ports
. . . . . . . . . . . . . . . . . . . .50
5.1.3
RxIN Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.1.4
RxOUT Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.1.5
RxDIR Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.1.6
INTED Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.1.7
INTF Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.1.8
INTE Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.1.9
Port Configuration Upon Power-Up
. . . . . . . . . . . . . . . .51
5.2
Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.3
Real-Time Timer (RTTMR) . . . . . . . . . . . . . . . . . . . .52
5.4
Multi-Function Timers (T1 and T2) . . . . . . . . . . . . . .54
5.4.1
Timers T1, T2 Operating Modes
. . . . . . . . . . . . . . . . . .54
5.4.2
T1 and T2 Timer Pin Assignments
. . . . . . . . . . . . . . . . .56
5.4.3
T1 and T2 Timer Registers
. . . . . . . . . . . . . . . . . . . . . .56
2
1.0 Product Highlights
Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . .57
Serializer/Deserializer (SERDES) . . . . . . . . . . . . . .58
5.6.1
SERDES TX/RX Buffers
. . . . . . . . . . . . . . . . . . . . . . . .58
5.6.2
SERDES Configuration
. . . . . . . . . . . . . . . . . . . . . . . . .58
5.6.3
SERDES Interrupts
. . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.6.4
Protocol Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.6.5
10base-T Ethernet
. . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.6.6
USB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.6.7
UART
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.6.8
SPI
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
5.6.9
GPSI
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
5.7
Analog to Digital Converter (ADC) . . . . . . . . . . . . . .72
5.7.1
ADC Reference Voltage
. . . . . . . . . . . . . . . . . . . . . . . .72
5.7.2
A/D Converter Registers
. . . . . . . . . . . . . . . . . . . . . . . .72
5.7.3
Using the A/D Converter
. . . . . . . . . . . . . . . . . . . . . . . .73
5.7.4
ADC Result Justification
. . . . . . . . . . . . . . . . . . . . . . . .73
5.8
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.8.1
CMPCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.9
Linear Feedback Shift Register (LFSR) . . . . . . . . . .74
5.9.1
LFSRCFG1 Register
. . . . . . . . . . . . . . . . . . . . . . . . . .75
5.9.2
LFSRCFG2 Register
. . . . . . . . . . . . . . . . . . . . . . . . . .76
5.9.3
LFSRCFG3 Register
. . . . . . . . . . . . . . . . . . . . . . . . . .76
5.9.4
DATAIN Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.9.5
DATAOUT Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.9.6
DOUT Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.9.7
FBx Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.9.8
POLYx Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.9.9
RESx Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.9.10
RESCMPx Registers
. . . . . . . . . . . . . . . . . . . . . . . . . .77
5.9.11
LFSR Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . .78
5.10
Parallel Slave Peripheral (PSP) . . . . . . . . . . . . . . . .79
5.10.1
PSPCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.11
External Memory Interface (IP2022 only) . . . . . . . . .80
5.11.1
EMCFG Register (IP2022 only)
. . . . . . . . . . . . . . . . . . .80
83
6.0 In-System Programming
84
7.0 Memory Reference
7.0.1
Registers (sorted by address)
. . . . . . . . . . . . . . . . . . . .84
7.0.2
Program Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.1
Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . .89
7.1.1
ADCCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.1.2
ADCTMR Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.1.3
CMPCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.1.4
EMCFG Register (IP2022 only)
. . . . . . . . . . . . . . . . . . .90
7.1.5
FCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
7.1.6
INTSPD Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.1.7
LFSRA Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.1.8
PSPCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.1.9
RTCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.1.10
SxINTE/SxINTF Register
. . . . . . . . . . . . . . . . . . . . . . .96
7.1.11
SxMODE Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.1.12
SxRCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.1.13
SxRCNT Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.1.14
SxRSYNC Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.1.15
SxSMASK Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.1.16
SxTCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.1.17
SxTMRH/SxTMRL Register
. . . . . . . . . . . . . . . . . . . . .100
7.1.18
SPDREG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.1.19
STATUS Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.1.20
T0CFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.1.21
TxCFG1H Register
. . . . . . . . . . . . . . . . . . . . . . . . . .102
7.1.22
TxCFG2H Register
. . . . . . . . . . . . . . . . . . . . . . . . . .103
7.1.23
TxCFG1L Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.1.24
TxCFG2L Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .104
7.1.25
TCTRL Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.1.26
XCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
106
8.0 Electrical Characteristics
8.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .106
8.2
DC Specifications: IP2022-120, IP2012-120 . . . . .107
8.3
DC Specifications: IP2022-160. . . . . . . . . . . . . . . .109
8.4
AC Specifications: IP2022-120, IP2012-120 . . . . . 111
8.5
AC Specifications: IP2022-160. . . . . . . . . . . . . . . . 112
8.6
Comparator DC and AC Specifications . . . . . . . . . 113
8.7
ADC 10-bit Converter DC and AC Specifications. . 113
114
9.0 Package Dimensions
9.1
PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.2
µBGA (available for IP2022-120 only) . . . . . . . . . . 115
116
10.0 Part Numbering
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