IP Core Supported Combinations of Number of Lanes and Data Rate....................................1-2
IP Core Theoretical Raw Aggregate Bandwidth.......................................................................... 1-2
Device Family Support................................................................................................................................ 1-3
IP Core Verification..................................................................................................................................... 1-3
Performance and Resource Utilization..................................................................................................... 1-4
Adding the Reconfiguration Controller......................................................................................2-13
Adding the External PLL...............................................................................................................2-15
Compiling the Full Design and Programming the FPGA.................................................................... 2-17
Creating a Signal Tap Debug File to Match Your Design Hierarchy ..................................................2-17
®
100G Interlaken IP Core Parameter Settings..................................................... 3-1
Number of Lanes.......................................................................................................................................... 3-1
Meta Frame Length in Words.....................................................................................................................3-2
Data Rate....................................................................................................................................................... 3-2
Transfer Mode Selection..............................................................................................................................3-6
Data Format.................................................................................................................................................. 3-7
Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers. The Altera
®
100G Interlaken MegaCore function implements the
Interlaken Protocol Specification, Revision 1.2 .
It
supports specific combinations of number of lanes (12 or 24) and lane rates from 6.25 gigabits per second
(Gbps) to 12.5 Gbps, on Stratix
®
V, Arria
®
V GZ, and Arria 10 devices, providing raw bandwidth of
123.75 Gbps to 150 Gbps.
Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of
lanes and lane speed. Other key features include flow control, low overhead framing, and extensive
integrity checking. The 100G Interlaken MegaCore function incorporates a physical coding sublayer
(PCS), a physical media attachment (PMA), and a media access control (MAC) block.
Figure 1-1: Typical Interlaken Application
Traffic
Management
Up to
150 Gbps
Interlaken
Interlaken
Interlaken
Interlaken
Switch
Fabric
FPGA/
ASIC
FPGA/
ASIC
Packet
Processing
Up to
150 Gbps
Interlaken
FPGA/
ASIC
To Line
Interface
Ethernet
MAC/Framer
Related Information
•
100G Interlaken MegaCore Function User Guide Archives
on page 11-1
•
Introduction to Altera IP Cores
Provides general information about all Altera FPGA IP cores, including parameterizing, generating,
upgrading, and simulating IP cores.
•
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
•
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
•
Interlaken Protocol Specification, Revision 1.2
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