Data Sheet No. PD60166 revS
IR2136/IR21362/IR21363/IR21365/
IR21366/IR21367/IR21368 (J&S) & (PbF)
Features
•
•
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
3-PHASE BRIDGE DRIVER
Packages
Fully operational to +600V
Tolerant to negative transient voltage - dV/dt immune
Gate drive supply range from 10 to 20V (IR2136/IR21368),
11.5 to 20V (IR21362) or 12 to 20V (IR21363/IR21365/
IR21366/IR21367)
Undervoltage lockout for all channels
28-Lead SOIC
Over-current shutdown turns off all six drivers
Independent 3 half-bridge drivers
28-Lead PDIP
Matched propagation delay for all channels
Cross-conduction prevention logic
44-Lead PLCC w/o 12 leads
Lowside outputs out of phase with inputs. High side
outputs out of phase (IR2136/IR21363/IR21365/
Feature Comparison: IR2136/IR21362/IR21363/
IR21366/IR21367/IR21368) or in phase
IR21365/IR21366/IR21367/IR21368
(IR21362) with inputs.
3.3V logic compatible
Part
IR2136 IR21362 IR21363 IR21365 IR21366 IR21367 IR21368
Lower di/dt gate driver for
Input Logic HIN, LIN HIN/LIN HIN, LIN HIN, LIN HIN, LIN HIN, LIN HIN,LIN
better noise immunity
400ns
Ton (typ.)
400ns
250ns
400ns
400ns
400ns
250ns
Externally programmable
Toff (typ.)
380ns
380ns
180ns
380ns
380ns
380ns
180ns
delay for automatic fault
V
IH
(typ.)
2.7V
2.0V
2.0V
2.7V
2.7V
2.7V
2.0V
clear
V
IL
(typ.)
1.7V
1.3V
1.3V
1.7V
1.7V
1.7V
1.3V
Also available LEAD-FREE
Vitrip+
4.3V
4.3V
0.46V
0.46V
0.46V
0.46V
4.3V
UV CC/BS+ 8.9V
UV CC/BS- 8.2V
10.4V
9.4V
11.2V
11.0V
11.2V
11.0V
11.2V
11.0V
11.2V
11.0V
8.9V
8.2V
Description
The IR2136/IR21362/IR21363/IR21365/IR21366/IR21367/IR21368(J&S) are high votage, high speed power MOSFET
and IGBT drivers with three independent high and low side referenced output channels for 3-phase applications.
Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS
or LSTTL outputs, down to 3.3V logic. A current trip function which terminates all six outputs can be derived from
an external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An
open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred.
Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC network
connected to the RCIN input. The output drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which
operates up to 600 volts.
Typical Connection
VCC
HIN1,2,3 / HIN1,2,3
LIN1,2,3
FAULT
VCC
HIN1,2,3 / HIN1,2,3
LIN1,2,3
HO1,2,3
FAULT
EN
VS1,2,3
VB1,2,3
up to 600V
(Refer to Lead Assign-
ments for correct pin con-
figuration). This/These
diagram(s) show electri-
cal connections only.
Please refer to our Appli-
cation
Notes
and
DesignTips for proper cir-
cuit board layout.
EN
RCIN
ITRIP
VSS
LO1,2,3
COM
TO
LOAD
IR2136(2)(3)(5)(6)(7)(8)
GND
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IR2136(2)(3)(5)(6)(7)(8)(J&S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.
Symbol
V
S
V
BS
V
HO
V
CC
V
SS
V
LO1,2,3
V
IN
Definition
High side offset voltage
High side floating supply voltage
High side floating output voltage
Low side and logic fixed supply voltage
Logic ground
Low side output voltage
Input voltage LIN,HIN,ITRIP, EN, RCIN
Min.
V
B1,2,3
- 25
-0.3
V
S1,2,3
- 0.3
-0.3
V
CC
- 25
-0.3
V
SS
- 0.3
Max.
V
B1,2,3
+ 0.3
625
V
B1,2,3
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
lower of
(V
SS
+ 15) or
V
CC
+ 0.3)
V
CC
+ 0.3
50
1.5
1.6
2.0
83
78
63
150
150
300
Units
V
V
FLT
dV/dt
P
D
FAULT output voltage
Allowable offset voltage slew rate
Package power dissipation @ T
A
≤
+25°C
Rth
JA
Thermal resistance, junction to ambient
(28 lead PDIP)
(28 lead SOIC)
( 44leadPLCC)
(28 lead PDIP)
(28 lead SOIC)
(44 lead PLCC)
T
J
T
S
T
L
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
V
SS
- 0.3
—
—
—
—
—
—
—
—
-55
—
V/ns
W
°C/W
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recom-
mended conditions. All voltage parameters are absolute referenced to COM. The VS offset rating is tested with all supplies
biased at 15V differential.
Symbol
V
B1,2,3
Definition
High side floating supply voltage
IR2136(8)
IR21362
IR2136(3)(5)(6)(7)
Min.
Max.
Units
V
S1,2,3
V
HO1,2,3
V
LO1,2,3
V
CC
High side floating supply offset voltage
High side output voltage
Low side output voltage
Low side and logic fixed supply voltage
IR2136(8)
IR21362
IR2136(3)(5)(6)(7)
V
SS
V
FLT
V
RCIN
Logic ground
FAULT output voltage
RCIN input voltage
V
S1,2,3 +
10 V
S1,2,3 +
20
V
S1,2,3 +
11.5 V
S1,2,3 +
20
V
S1,2,3 +
12 V
S1,2,3 +
20
Note 1
600
V
S1,2,3
V
B1,2,3
0
V
CC
10
20
11.5
20
12
20
-5
5
V
SS
V
CC
V
SS
V
CC
V
Note 1: Logic operational for V
S
of COM -5V to COM +600V. Logic state held for V
S
of COM -5V to COM -V
BS
.
(Please refer to the Design Tip DT97-3 for more details).
Note 2: All input pins and the ITRIP pin are internally clamped with a 5.2V zener diode.
2
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IR2136(2)(3)(5)(6)(7)(8)(J&S) & (PbF)
Recommended Operating Conditions cont.
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recom-
mended conditions. All voltage parameters are absolute referenced to COM. The VS offset rating is tested with all supplies
biased at 15V differential.
Symbol
V
ITRIP
V
IN
T
A
Definition
ITRIP input voltage
Logic input voltage
LIN
, HIN (IR2136,IR21363(5)(6)(7)(8)),
HIN(IR21362), EN
Ambient temperature
Min.
V
SS
V
SS
-40
Max.
V
SS
+5
V
SS
+5
125
Units
V
o
C
Note 2: All input pins and the ITRIP pin are internally clamped with a 5.2V zener diode.
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
1,2,3) = 15V unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to V
SS
and
are applicable to all six channels (H
S
1,2,3 and L
S
1,2,3). The V
O
and I
O
parameters are referenced to COM and V
S
1,2,3
and are applicable to the respective output leads: H
O1,2,3
and L
O1,2,3.
Symbol
V
IH
Definition
Logic “0” input voltage LIN1,2,3, HIN1,2,3
IR2136(3)(5)
Logic “1” input voltage HIN1,2,3
IR21362
Logic “0” input voltage LIN1,2,3, HIN1,2,3
Min. Typ. Max. Units Test Conditions
3.0
—
—
V
IL
IR21366(7)(8)
Logic “1” input voltage LIN1,2,3, HIN1,2,3
IR2136(3)(5)
Logic “0” input voltage HIN1,2,3
IR21362
Logic “0” input voltage LIN1,2,3, HIN1,2,3
IR21366(7)(8)
2.5
—
—
—
—
0.8
—
—
0.8
—
—
—
0.46
4.30
0.07
.15
8
3
0.9
0.4
8.9
10.4
11.1
0.8
3
—
0.55
4.75
—
—
—
—
1.4
0.6
9.8
11.2
11.6
I
O
= 20 mA
I
O
= 20 mA
V
V
EN,TH+
V
EN,TH-
V
IT,TH+
EN positive going threshold
EN negative going threshold
ITRIP positive going threshold
IR2136(2)(3)(6)
IR21365(7)(8)
0.37
3.85
—
—
—
—
—
—
8.0
9.6
10.6
V
IT,HYS
ITRIP input hysteresis
IR2136(2)(3)(6)
IR21365(7)(8)
V
RCIN,TH+
V
RCIN,HYS
V
OH
V
OL
V
CCUV+
V
BSUV+
RCIN positive going threshold
RCIN input hysteresis
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
V
CC
and V
BS
supply undervoltage
positive going threshold
IR2136(8)
IR21362
IR21363(5)(6)(7)
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IR2136(2)(3)(5)(6)(7)(8)(J&S) & (PbF)
Static Electrical Characteristics cont.
V
BIAS
(V
CC
, V
BS
1,2,3) = 15V unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to V
SS
and
are applicable to all six channels (H
S
1,2,3 and L
S
1,2,3). The V
O
and I
O
parameters are referenced to COM and V
S
1,2,3
and are applicable to the respective output leads: H
O1,2,3
and L
O1,2,3.
Symbol
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
LK
I
QBS
I
QCC
V
IN, CLAMP
I
LIN+
I
LIN-
I
HIN+
Definition
V
CC
and V
BS
supply undervoltage
negative going threshold
IR2136(8)
IR21362
IR21363(5)(6)(7)
V
CC
and V
BS
supply undervoltage
IR2136
lockout hysteresis
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Input clamp voltage (HIN, LIN, ITRIP and EN)
Min. Typ. Max. Units Test Conditions
7.4
8.6
10.4
0.3
0.5
—
—
—
—
4.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
120
250
—
—
8.2
9.4
10.9
0.7
1.0
0.2
—
70
1.6
5.2
200
0
100
0
200
30
0
100
0
30
0
30
0
0
200
350
50
50
9.0
10.2
11.4
—
—
—
50
120
2.3
5.5
300
1
220
1
300
100
1
220
1
100
1
100
1
1
—
—
100
100
mA
V
ITRIP
= 5V
V
ITRIP
= 0V
V
ENABLE
= 5V
V
ENABLE
= 0V
V
RCIN
= 0V or 15V
V
O
=0V, PW
≤
10
µs
V
O
=15V, PW
≤10
µs
µA
V
HIN
= 0V
V
HIN
= 5V
V
LIN
= 0V
V
IR21362
IR21363(5)
µA
mA
V
V
B1,2,3
=V
S1,2,3
=600V
V
IN
= 0V or 5V
I
IN
=100µA
V
LIN
= 5V
Input bias current (LOUT = HI)
Input bias current (LOUT = LO)
Input bias current (HOUT = HI)
IR2136(2)(3)(5)
IR21366(7)(8)
IR2136(2)(3)(5)
IR21366(7)(8)
IR2136(3)(5)
IR21362
IR21366(7)(8)
IR2136(3)(5)
IR21362(6)(7)(8)
I
HIN-
I
ITRIP+
I
ITRIP-
I
EN+
I
EN-
I
RCIN
I
O+
I
O-
R
ON,RCIN
R
ON,FLT
Input bias current (HOUT = LO)
“high” ITRIP input bias current
“low” ITRIP input bias current
“high” ENABLE input bias current
“low” ENABLE input bias current
RCIN input bias current
Output high short circuit pulsed current
Output low short circuit pulsed current
RCIN low on resistance
FAULT low on resistance
Ω
4
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IR2136(2)(3)(5)(6)(7)(8)(J&S) & (PbF)
Dynamic Electrical Characteristics
V
CC
= V
BS
= V
BIAS
= 15V, V
S1,2,3
= V
SS
= COM, TA = 25
o
C and C
L
= 1000 pF unless otherwise specified.
Symbol
ton
toff
tr
tf
tEN
tITRIP
tbl
tFLT
tFILIN
tFLTCLR
DT
MT
MDT
PM
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
ENABLE low to output
shutdown propagation delay
ITRIP blanking time
ITRIP to FAULT propagation delay
Input filter time (HIN, LIN, EN)
(IR2136(2)(3)(5)(8) only)
FAULT clear time RCIN: R=2meg, C=1nF
Deadtime
Matching delay ON and OFF
Matching delay, max (ton,toff) - min (ton,toff),
(ton,toff are applicable to all 3 channels)
Output pulse width matching, PWin -PWout (fig.2)
IR2136(2)(3)(5)(8)
IR21366(7)
IR2136(2)(3)(5)(8)
IR21366(7)
IR2136(2)(3)(5)(8)
IR21366(7)
Min.
300
—
250
—
—
—
300
100
500
100
400
100
1.3
220
—
—
—
Typ.
425
250
400
180
125
50
450
250
750
150
600
200
1.65
290
40
25
40
Max. Units Test Conditions
550
—
550
—
190
75
600
400
1000
—
800
—
2
360
75
70
75
nS
mS
nS
V
IN,
V
EN
= 0V or 5V
V
ITRIP
= 5V
V
IN
= 0V or 5V
V
ITRIP
= 5V
V
IN
= 0V or 5V
V
ITRIP
= 5V
V
IN
= 0 & 5V
V
IN
= 0V or 5V
V
ITRIP
= 0V
V
IN
= 0 & 5V
External dead
time
>400nsec
V
IN
= 0 & 5V
ITRIP to output shutdown propagation delay
NOTE: For high side PWM, HIN pulse width must be
≥ 1µsec
VCC
<UVCC
15V
15V
15V
15V
VBS
X
<UVBS
15V
15V
15V
ITRIP
X
0V
0V
>VITRIP
0V
ENABLE
X
5V
5V
5V
0V
FAULT
0 (note 1)
high imp
high imp
0 (note 2)
high imp
LO1,2,3
0
LIN1,2,3
LIN1,2,3
0
0
HO1,2,3
0
0
HIN1,2,3
0
0
Note:
A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
Note 1:
UVCC is not latched, when VCC>UVCC, FAULT returns to high impedance.
Note 2:
When ITRIP <V
ITRIP
, FAULT returns to high-impedance after RCIN pin becomes greater than 8V (@ VCC = 15V)
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