Data Sheet No.PD60231 revB
IR3621 & (PbF)
2-PHASE / DUAL SYNCHRONOUS PWM CONTROLLER WITH
OSCILLATOR SYNCHRONIZATION AND PRE-BIAS STARTUP
FEATURES
Dual Synchronous Controller with 180
Out of Phase Operation
Configurable to 2-Independent Outputs or
Current Share Single Output
Voltage Mode Control
Current Sharing Using Inductor's DCR
Selectable Hiccup or Latched Current
Limit using MOSFET's R
DS(on)
sensing
Latched Over-Voltage Protection
Pre-Bias Start Up
Programmable Switching Frequency up to 500KHz
Two Independent Soft-Starts/Shutdowns
Precision Reference Voltage 0.8V
Power Good Output
External Frequency Synchronization
Thermal Protection
DESCRIPTION
The IR3621 IC combines a dual synchronous buck control-
ler and drivers, providing a cost-effective, high performance
and flexible solution. The IR3621 operates in 2-Phase mode
to produce either 2-independent output voltages or current
share single output for high current application. The 180
out-of-phase operation allows the reduction of input and
output capacitance.
Other key features include two independently programmable
soft-start functions to allow system level sequencing of out-
put voltages in various configurations. The pre-bias protec-
tion feature prevents the discharge of the output voltage and
possible damage to the load during start-up when a pre-
existing voltage is present at the output. Programmable
switching frequency up to 500KHz per phase allows flexibil-
ity to tune the operation of the IC to meet system level re-
quirements, and synchronization allows the simplification
of system level filter design. Protection features such as
selectable hiccup or latched current limit, and under voltage
lock-out are provided to give required system level security
in the event of a fault condition.
APPLICATIONS
Embedded Networking & Telecom Systems
Distributed Point-of-Load Power Architectures
2-Phase Power Supply
Graphics Card
DDR Memory Applications
Vin
Vin
Rt
Comp1
HDrv1
OCSet1
LDrv1
PGnd1
Rt
Comp1
HDrv1
OCSet1
LDrv1
PGnd1
Vout1
Comp2
SS1 / SD
SS2 / SD
Gnd
IR3621
HDrv2
OCSet2
LDrv2
PGnd2
Vin
Vout
Comp2
SS1 / SD
SS2 / SD
IR3621
HDrv2
OCSet2
LDrv2
Vin
Vout2
Gnd
PGnd2
Current share, single output configuration
2-independent output voltage configuration
Figure 1 - Typical application of IR3621 in current share single output and 2-independent output voltage configuration
ORDERING INFORMATION
PKG
DESIG
M
M
F
F
PART
NUMBER
IR3621M
IR3621MTR
IR3621F
IR3621FTR
LEADFREE
PART NUMBER
IR3621MPbF
IR3621MTRPbF
IR3621FPbF
IR3621FTRPbF
PIN
COUNT
32
32
28
28
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PARTS
PER TUBE
73
------
50
------
PARTS
PER REEL
------
6000
------
2500
T&R
Orientation
Fig A
1
IR3621 & (PbF)
ABSOLUTE MAXIMUM RATINGS
Vcc, V
CL
Supply Voltage ...........................................
VcH1 and VcH2 Supply Voltage ................................
PGOOD....................................................................
Storage Temperature Range ......................................
Junction Temperature Range .....................................
ESD Classification ...................................................
-0.5V To 16V
-0.5V To 25V
-0.5V To 16V
-55°C To 150°C
-40°C To 150°C
JEDEC, JESD22-A114
Caution:
Stresses above those listed in “Absolute Maximum Rating” may cause permanent damage to the device. These are stress
ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifica-
tions is not implied. Exposure to “Absolute Maximum Rating” conditions for extended periods may affect device reliability
RECOMMENDED OPERATING CONDITIONS
Parameter
Vcc
VcH1,2
Fs
Tj
Definition
Supply Voltage
Supply Voltage
Operating Frequency
Junction Temperature
Min
5.5
10
200
-40
Max
14.5
20
500
125
Units
V
V
kHz
°C
PACKAGE INFORMATION
IR3621F
28-PIN TSSOP (F)
PGood
1
V
CC
2
V
OUT3
3
Rt
4
V
SEN2
5
Fb2
6
Comp2
7
SS2 / SD
8
OCSet2
9
VcH2
10
HDrv2
11
PGnd2
12
LDrv2
13
V
CL
14
28
Gnd
27
V
REF
26
V
P2
25
Hiccup
24
Sync
23
V
SEN1
22
Fb1
21
Comp1
20
SS1 / SD
19
OCSet1
18
VcH1
17
HDrv1
16
PGnd1
15
LDrv1
IR3621M & IR3621MPbF
32-Lead MLPQ 5mmx5mm (M)
PG
ood
Gn
d
V
R
UT
3
NC
Vc
c
EF
32
Rt
V
SEN2
Fb2
1
2
31
30
29
28 27
V
P2
26
V
O
25
24 Hiccup
23 Sync
22 V
SEN1
3
Comp2 4
SS2/SD2
5
NC
21 Fb1
20 Comp1
19 SS1/SD1
18 OCSet1
17
VcH1
16
Pad
OCSet2 6
VCH2
HDrv2
7
8
9
10
11
12
13
14
15
PG
nd2
LD
rv2
LD
rv1
PG
nd1
NC
θ
JA
= 75.5
°C/W
θ
JC
=13.3
°C/W
θ
JA
= 36.0
°C/W
θ
JC
= 1.0
°C/W
Exposed pad on underside is connected to a copper
pad through vias for 4-layer PCB board design.
2
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HD
rv1
NC
V
C
L
IR3621 & (PbF)
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=12V, VcH1=VcH2=V
CL
=12V and 0°C<T
j
<125°C.
PARAMETER
Output Voltage Accuracy
Feedback Voltage
SYMBOL
V
Fb1 ,
V
Fb2
MLPQ
Accuracy
TSSOP
Tj=25°C
0°C <T
j
< 125°C
-40°C <T
j
< 125°C
Tj=25°C
0°C <T
j
< 125°C
-40°C <T
j
< 125°C
-1
-1.35
-2.5
-1.35
-1.65
-3.0
4.7
1
3.5
0.75
10
15
15
10
6
6
22
28
15
25
25
15
10
10
35
0.25
4.0
TEST CONDITION
MIN
TYP
0.80
+1
+1.35
+1.35
+1.35
+1.65
+1.65
5.3
MAX
UNITS
V
%
%
%
%
%
%
V
V
V
V
mA
mA
mA
mA
mA
mA
µA
V
V
V
µA
µmho
µmho
µA
mV
V
kHz
V
%
ns
%
kHz
ns
V
V
UVLO Section
UVLO Threshold - Vcc
UVLO
V
CC
Supply Ramping Up
Supply Ramp Up and Down
UVLO Hysteresis - Vcc
UVLO Threshold - VcH1,2
UVLO
V
C
H1,2
Supply Ramping Up
Supply Ramp Up and Down
UVLO Hysteresis - VcH1,2
Supply Current Section
Vcc Dynamic Supply Current
Dyn I
CC
Freq=300kHz, C
L
=1500pF
VcH1 & VcH2 Dynamic Current
Dyn I
CH
Freq=300kHz, C
L
=1500pF
V
CL
Dynamic Supply Current
Dyn I
CL
Freq=300kHz, C
L
=1500pF
SS=0V
Vcc Static Supply Current
I
CCQ
SS=0V
VcH1/VcH2 Static Current
I
CHQ
SS=0V
V
CL
Static Supply Current
I
CLQ
Soft-Start / SD Section
SS
IB
SS=0V
Charge Current
SD
Shutdown Threshold
Power Good Section
PG
FB1,2L
V
SENS1,2
Ramping Down
V
SENS1,2
Lower Trip Point
PG
(Voltage)
I
SINK
=2mA
PGood Output Low Voltage
Error Amp Section
I
FB1,2
SS=3V
Fb Voltage Input Bias Current
g
m1
Transconductance 1
g
m2
Transconductance 2
I
(E/A)1,2
Error Amp Source/Sink Current
V
OS(ERR)
Fb
1,2
to V
REF
Input Offset Voltage for E/A1,2
VP2
Note2
VP2 Voltage Range
Oscillator Section
Freq
Rt
(SET)
to 30.9K
Frequency
V
RAMP
Note2
Ramp Amplitude
Dmin
Fb=1V
Min Duty Cycle
Puls(ctrl) F
SW
=300kHz, Note2
Min Pulse Width
Dmax
Fb=0.6V, F
SW
=200kHz
Max Duty Cycle
Sync(Fs) 20% above free running freq
Synch Frequency Range
Sync(puls)
Synch Pulse Duration
Sync(H)
Synch High Level Threshold
Sync(L)
Synch Low Level Threshold
0.8
V
REF
0.9
V
REF
0.95
V
REF
0.1
0.5
-0.1
1400
1400
60
-4
0.4
255
1.25
0
150
86.5
1200
200
2
300
0.6
-0.5
2500
2500
140
+4
Vcc-2
345
100
0
Note1: Cold temperature performance is guaranteed via correlation using statistical quality control. Not 100% tested in production.
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3
IR3621 & (PbF)
PARAMETER
V
OUT3
Internal Regulator
Output Voltage
Output Current
Protection Section
OVP Trip Threshold
OVP Fault Prop Delay
OCSET Current
Hiccup Duty Cycle
Hiccup High Level Threshold
Hiccup Low Level Threshold
Thermal Shutdown Trip Point
Thermal Shutdown Hysteresis
Output Drivers Section
LO Drive Rise Time
HI Drive Rise Time
LO Drive Fall Time
Hi Drive Fall Time
Dead Band Time
SYMBOL
TEST CONDITION
MIN
5.8
44
OVP
Output forced to 1.25V
REF
OVP
(delay)
Note2
I
OCSet
Hiccup pin pulled high, Note2
Note2
Note2
Note2
Note2
T
r(LO)
T
r(HI)
T
f(LO)
T
f(HI)
T
DB
C
L
=1500pF,Figure 2
C
L
=1500pF, Figure 2
C
L
=1500pF,Figure 2
C
L
=1500pF,Figure 2
See Figure 2
TYP
6.25
MAX
6.7
UNITS
V
mA
V
µs
µA
%
V
V
C
C
ns
ns
ns
ns
ns
1.1
V
REF
1.15
V
REF
1.2
V
REF
5
16
20
24
5
2
0.8
140
20
18
18
25
25
50
50
50
50
50
100
Note 2:
Guaranteed by design but not tested for production.
Tr
9V
High Side Driver
(HDrv)
2V
Tf
Tr
9V
Low Side Driver
(LDrv)
2V
Deadband
H_to_L
Tf
Deadband
L_to_H
Figure 2 - Rise Time, Fall Time and Deadband for Driver Section
4
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IR3621 & (PbF)
PIN DESCRIPTIONS
TSSOP
MLPQ
PIN SYMBOL
PIN DESCRIPTION
1
2
3
4
5,23
6,22
7,21
8
20
9,19
10,18
11,17
12,16
13,15
14
24
25
26
27
28
Power Good pin. Low when any of the outputs fall 10% below the set voltages.
Supply voltage for the internal blocks of the IC. The Vcc slew rate should be
<0.1V/us.
Output of the internal LDO. Connect a 1.0uF capacitor from this pin to ground.
V
OUT3
31
Connecting a resistor from this pin to ground sets the oscillator frequency.
Rt
1
Sense pins for OVP and PGood. For current share tie these pins together.
V
SEN2
, V
SEN1
2,22
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is con-
Fb2,Fb1
3,21
nected to a resistor divider to set the output voltage and Fb2 is connected to
programming resistor to achieve current sharing. In independent 2-channel mode,
these pins work as feedback inputs for each channel.
4,20 Comp2, Comp1 Compensation pins for the error amplifiers.
These pins provide user programmable soft-start function for each outputs.
SS2 / SD
5
Connect external capacitors from these pins to ground to set the start up time
SS1 / SD
19
for each output. These outputs can be shutdown independently by pulling the
respective pins below 0.3V. During shutdown both MOSFETs will be turned off.
For current share mode SS2 must be floating.
6,18 OCSet2,OCSet1 A resistor from these pins to switching point will set current limit threshold.
VcH2, VcH1 Supply voltage for the high side output drivers. These are connected to voltages
7,17
that must be typically 6V higher than their bus voltages. A 0.1µF high fre-
quency capacitor must be connected from these pins to PGND to provide peak
drive current capability.
HDrv2, HDrv1 Output drivers for the high side power MOSFETs.
Note3
8,16
10,14 PGnd2, PGnd1 These pins serve as the separate grounds for MOSFET drivers and should be
connected to the system’s ground plane.
LDrv2, LDrv1 Output drivers for the synchronous power MOSFETs.
11,13
Supply voltage for the low side output drivers.
V
CL
12
The internal oscillator can be synchronized to an external clock via this pin.
Sync
23
When pulled High, it puts the device current limit into a hiccup mode. When
Hiccup
24
pulled Low, the output latches off, after an overcurrent event.
Non-inverting input to the second error amplifier. In the current sharing mode, it
V
P2
26
is connected to the programming resistor to achieve current sharing. In inde-
pendent 2-channel mode it is connected to V
REF
pin when Fb2 is connected to
the resistor divider to set the output voltage.
Reference Voltage. The drive capability of this pin is about 2µA.
V
REF
27
Analog ground for internal reference and control circuitry.
Gnd
28
N/C
9,15,25.32
No Connect
29
30
PGood
Vcc
Note3:
The negative voltage at these pins may cause instability for the gate drive circuits. To prevent this, a low
forward voltage drop diode (Schottky) is required between these pins and power ground.
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