notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equip-
ment, aerospace systems, or for other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best
performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services described
herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
09/11/09
3
IS24C01B IS24C02B
FUNCTIONAL BLOCK DIAGRAM
Vcc
8
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
SDA
SCL
WP
5
7
X
DECODER
6
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
EEPROM
ARRAY
A0
A1
A2
1
2
3
WORD ADDRESS
COUNTER
Y
DECODER
GND
4
ACK
nMOS
Clock
DI/O
>
DATA
REGISTER
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
9/11/09
IS24C01B IS24C02B
PIN CONFIGURATION
8-Pin SOIC, TSSOP
8-pad UDFn, DFn
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
(Top View)
PIn DESCRIPTIOnS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire-Or'ed with other open drain or
open collector outputs. The SDA bus
requires
a pullup resistor
to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs. The
IS24C01B/02B uses the A0, A1, and A2 for hardware addressing
and a total of 8 devices may be used on a single bus system.
When the A0, A1, or A2 inputs are left floating, the input
internally defaults to zero.
WP
WP is the Write Protect pin. If the WP pin is tied to V
cc
on
the EEPROM, the entire array becomes Write Protected
(Read only). When WP is tied to GND or left floating normal
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微控制器 MCU
